Silicon rich barrier layers for integrated circuit devices

Claim 1

A method of forming a semiconductor device, comprising: forming a first silicon rich barrier layer comprising silicon and nitrogen proximate to a semiconductor substrate; forming a polysilicon film proximate to said first silicon rich barrier layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a second silicon rich barrier layer comprising silicon and nitrogen proximate to said polysilicon film; and forming a conductive layer proximate to said second silicon rich barrier layer, wherein: said first silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said substrate is significantly impeded by said first silicon rich barrier layer; and said second silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 2

A method of forming a semiconductor device, comprising: forming a first silicon rich barrier layer comprising silicon and nitrogen proximate to a semiconductor substrate; forming a polysilicon film proximate to said first silicon rich barrier layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a second silicon rich barrier layer comprising silicon and nitrogen proximate to said polysilicon film; and forming a conductive layer proximate to said second silicon rich barrier layer, wherein: said first silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said substrate is significantly impeded by said first silicon rich barrier layer; and said second silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 24

A method of forming a semiconductor device, comprising: forming a first silicon rich silicon nitride layer proximate to a semiconductor substrate, wherein said first silicon rich silicon nitride layer has a silicon molar percentage of about 65 to about 90 percent; forming a polysilicon film proximate to said first silicon rich silicon nitride layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a second silicon rich silicon nitride layer proximate to said polysilicon film, wherein said second silicon rich silicon nitride layer has a silicon molar percentage of about 65 to about 90 percent; and forming a conductive layer proximate to said second silicon rich silicon nitride layer, wherein: said first silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said substrate is significantly impeded by said first silicon rich barrier layer; and said second silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 25

A method of forming a semiconductor device, comprising: forming a first silicon rich silicon nitride layer proximate to a semiconductor substrate, wherein said first silicon rich silicon nitride layer has a silicon molar percentage of about 65 to about 90 percent; forming a polysilicon film proximate to said first silicon rich silicon nitride layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a second silicon rich silicon nitride layer proximate to said polysilicon film, wherein said second silicon rich silicon nitride layer has a silicon molar percentage of about 65 to about 90 percent; and forming a conductive layer proximate to said second silicon rich silicon nitride layer, wherein: said first silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said substrate is significantly impeded by said first silicon rich barrier layer; and said second silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 30

A method of forming a semiconductor device, comprising: forming a first silicon rich silicon oxynitride layer proximate to a semiconductor substrate, wherein said first silicon rich silicon oxynitride layer has a silicon molar percentage of about 55 to about 90 percent; forming a polysilicon film proximate to said first silicon rich silicon oxynitride layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a second silicon rich silicon oxynitride layer proximate to said polysilicon film, wherein said second silicon rich silicon oxynitride layer has a silicon molar percentage of about 55 to about 90 percent; and forming a conductive layer proximate to said second silicon rich silicon oxynitride layer, wherein: said first silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said substrate is significantly impeded by said first silicon rich barrier layer; and said second silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 31

A method of forming a semiconductor device, comprising: forming a first silicon rich silicon oxynitride layer proximate to a semiconductor substrate, wherein said first silicon rich silicon oxynitride layer has a silicon molar percentage of about 55 to about 90 percent; forming a polysilicon film proximate to said first silicon rich silicon oxynitride layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a second silicon rich silicon oxynitride layer proximate to said polysilicon film, wherein said second silicon rich silicon oxynitride layer has a silicon molar percentage of about 55 to about 90 percent; and forming a conductive layer proximate to said second silicon rich silicon oxynitride layer, wherein: said first silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said substrate is significantly impeded by said first silicon rich barrier layer; and said second silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 32

A method of forming semiconductor device, comprising: forming a gate oxide layer over a semiconductor substrate; forming a first silicon rich barrier layer comprising silicon and nitrogen over said gate oxide layer, wherein: said first silicon rich barrier layer is selected from the group consisting of silicon rich silicon nitride having a silicon molar percentage between about 65 to about 90 percent and silicon rich silicon oxynitride having a silicon molar percentage between about 55 to about 90 percent; and said first silicon rich barrier layer is about 50 Å to about 100 Å thick; forming a polysilicon film over said first silicon barrier layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a second silicon rich barrier layer comprising silicon and nitrogen over said polysilicon film, wherein: said second silicon rich barrier layer is selected from the group consisting of silicon rich silicon nitride having a silicon molar percentage between about 65 to about 90 percent and silicon rich silicon oxynitride having a silicon molar percentage between about 55 to about 90 percent; and said second silicon rich barrier layer is about 50 Å to about 100 Å thick; and forming a conductive over said second silicon rich barrier layer, wherein: said conductive layer comprises tungsten silicide; said first silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said substrate is significantly impeded by said first silicon rich barrier layer; and said second silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 33

A method of forming semiconductor device, comprising: forming a gate oxide layer over a semiconductor substrate; forming a first silicon rich barrier layer comprising silicon and nitrogen over said gate oxide layer, wherein: said first silicon rich barrier layer is selected from the group consisting of silicon rich silicon nitride having a silicon molar percentage between about 65 to about 90 percent and silicon rich silicon oxynitride having a silicon molar percentage between about 55 to about 90 percent; and said first silicon rich barrier layer is about 50 Å to about 100 Å thick; forming a polysilicon film over said first silicon barrier layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a second silicon rich barrier layer comprising silicon and nitrogen over said polysilicon film, wherein: said second silicon rich barrier layer is selected from the group consisting of silicon rich silicon nitride having a silicon molar percentage between about 65 to about 90 percent and silicon rich silicon oxynitride having a silicon molar percentage between about 55 to about 90 percent; and said second silicon rich barrier layer is about 50 Å to about 100 Å thick; and forming a conductive over said second silicon rich barrier layer, wherein: said conductive layer comprises tungsten silicide; said first silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said substrate is significantly impeded by said first silicon rich barrier layer; and said second silicon rich silicon barrier layer is arranged such that migration of said first and second type dopants from said polysilicon film to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 34

A method of forming a memory cell, comprising: forming a first type well a semiconductor substrate; forming a second type well in said semiconductor substrate; forming a second type region defined in said first type well; forming a first type region defined in said second type well; arranging an isolation region to isolate said first type active region from said second type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a first silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer.

Claim 35

A method of forming a memory cell, comprising: forming a first type well a semiconductor substrate; forming a second type well in said semiconductor substrate; forming a second type region defined in said first type well; forming a first type region defined in said second type well; arranging an isolation region to isolate said first type active region from said second type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises a first region having a first type dopant and a second region having a second type dopant; forming a first silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer.

Claim 42

A method of forming a memory cell, comprising: forming a P well in a semiconductor substrate; forming an N well in said semiconductor substrate; forming an NMOS transistor defining an N type active region in said P well; forming a PMOS transistor defining a P type active region in said N well; arranging an isolation region to isolate said N type active region from said P type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said NMOS transistor and a P+ polysilicon layer forming a portion of said PMOS transistor; forming a first silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein said first silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich barrier layer; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein said second silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 43

A method of forming a memory cell, comprising: forming a P well in a semiconductor substrate; forming an N well in said semiconductor substrate; forming an NMOS transistor defining an N type active region in said P well; forming a PMOS transistor defining a P type active region in said N well; arranging an isolation region to isolate said N type active region from said P type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said NMOS transistor and a P+ polysilicon layer forming a portion of said PMOS transistor; forming a first silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein said first silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich barrier layer; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein said second silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 57

A method of forming a memory cell, comprising: forming a P well in a semiconductor substrate; forming an N well in said semiconductor substrate; forming an NMOS transistor defining an N type active region in said P well; forming a PMOS transistor defining a P type active region in said N well; arranging an isolation region to isolate said N type active region from said P type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said NMOS transistor and a P+ polysilicon layer forming a portion of said PMOS transistor; forming a first silicon rich silicon nitride layer in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein: said first silicon rich silicon nitride layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich silicon nitride layer; and said first silicon rich silicon nitride layer has a silicon molar percentage of about 65 to about 90 percent; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein: said second silicon rich silicon nitride layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich silicon nitride layer; and said second silicon rich silicon nitride layer has a silicon molar percentage of about 65 to about 90 percent.

Claim 58

A method of forming a memory cell, comprising: forming a P well in a semiconductor substrate; forming an N well in said semiconductor substrate; forming an NMOS transistor defining an N type active region in said P well; forming a PMOS transistor defining a P type active region in said N well; arranging an isolation region to isolate said N type active region from said P type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said NMOS transistor and a P+ polysilicon layer forming a portion of said PMOS transistor; forming a first silicon rich silicon nitride layer in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein: said first silicon rich silicon nitride layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich silicon nitride layer; and said first silicon rich silicon nitride layer has a silicon molar percentage of about 65 to about 90 percent; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein: said second silicon rich silicon nitride layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich silicon nitride layer; and said second silicon rich silicon nitride layer has a silicon molar percentage of about 65 to about 90 percent.

Claim 59

A method of forming a memory cell, comprising: forming a P well in a semiconductor substrate; forming an N well in said semiconductor substrate; forming an NMOS transistor defining an N type active region in said P well; forming a PMOS transistor defining a P type active region in said N well; arranging an isolation region to isolate said N type active region from said P type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said NMOS transistor and a P+ polysilicon layer forming a portion of said PMOS transistor; forming a first silicon rich silicon oxynitride layer in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein: said first silicon rich silicon oxynitride layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich silicon oxynitride layer; and said first silicon rich silicon oxynitride layer has a silicon molar percentage of about 55 to about 90 percent; and forming a second silicon rich silicon oxynitride layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein: said second silicon rich silicon oxynitride layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich silicon oxynitride layer; and said second silicon rich silicon oxynitride layer has a silicon molar percentage of about 55 to about 90 percent.

Claim 60

A method of forming a memory cell, comprising: forming a P well in a semiconductor substrate; forming an N well in said semiconductor substrate; forming an NMOS transistor defining an N type active region in said P well; forming a PMOS transistor defining a P type active region in said N well; arranging an isolation region to isolate said N type active region from said P type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said NMOS transistor and a P+ polysilicon layer forming a portion of said PMOS transistor; forming a first silicon rich silicon oxynitride layer in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein: said first silicon rich silicon oxynitride layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich silicon oxynitride layer; and said first silicon rich silicon oxynitride layer has a silicon molar percentage of about 55 to about 90 percent; and forming a second silicon rich silicon oxynitride layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein: said second silicon rich silicon oxynitride layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich silicon oxynitride layer; and said second silicon rich silicon oxynitride layer has a silicon molar percentage of about 55 to about 90 percent.

Claim 61

A method of forming a memory cell, comprising: forming a P well in a semiconductor substrate; forming an N well in said semiconductor substrate; forming an NMOS transistor defining an N type active region in said P well; forming a PMOS transistor defining a P type active region in said N well; arranging an isolation region to isolate said N type active region from said P type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying tungsten silicide conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said NMOS transistor and a P+ polysilicon layer forming a portion of said PMOS transistor; forming a first silicon rich barrier layer selected from the group consisting of silicon rich silicon nitride having a silicon molar percentage between about 65 to about 90 percent and silicon rich silicon oxynitride having a silicon molar percentage between about 55 to about 90 percent formed in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein: said first silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich barrier layer; and said first silicon rich barrier layer is about 50 Å to about 100 Å thick; and forming a second silicon rich barrier layer selected from the group consisting of silicon rich silicon nitride having a silicon molar percentage between about 65 to about 90 percent and silicon rich silicon oxynitride having a silicon molar percentage between about 55 to about 90 percent formed in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein: said second silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich barrier layer; and said second silicon rich barrier layer is about 50 Å to about 100 Å thick.

Claim 62

A method of forming a memory cell, comprising: forming a P well in a semiconductor substrate; forming an N well in said semiconductor substrate; forming an NMOS transistor defining an N type active region in said P well; forming a PMOS transistor defining a P type active region in said N well; arranging an isolation region to isolate said N type active region from said P type active region; forming a polycilicide gate electrode structure composed of a polysilicon film and an overlying tungsten silicide conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said NMOS transistor and a P+ polysilicon layer forming a portion of said PMOS transistor; forming a first silicon rich barrier layer selected from the group consisting of silicon rich silicon nitride having a silicon molar percentage between about 65 to about 90 percent and silicon rich silicon oxynitride having a silicon molar percentage between about 55 to about 90 percent formed in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein: said first silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich barrier layer; and said first silicon rich barrier layer is about 50 Å to about 100 Å thick; and forming a second silicon rich barrier layer selected from the group consisting of silicon rich silicon nitride having a silicon molar percentage between about 65 to about 90 percent and silicon rich silicon oxynitride having a silicon molar percentage between about 55 to about 90 percent formed in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein: said second silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich barrier layer; and said second silicon rich barrier layer is about 50 Å to about 100 Å thick.

Claim 63

A method of fabricating a memory cell array by arranging a plurality of SRAM cells in rows and columns and connecting each SRAM cell of said array to a word line and to a pair of bit lines, wherein each of said SRAM cells is fabricated by: providing a semiconductor substrate; forming a P well in said semiconductor substrate; forming an N well in said semiconductor substrate; providing a flip-flop including two access transistors and a pair of cross coupled inverters, wherein each pair of cross-coupled inverters includes a pull up transistor defining a P type active region in said N well and a pull down transistor defining an N type active region in said P well; arranging an isolation region to isolate said N type active region from said P type active region; providing a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said pull down transistor and a P+ polysilicon layer forming a portion of said pull up transistor; forming a first silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein said first silicon rich barrier layer is arranged such that migration of N+ and P+dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich barrier layer; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein said second silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 64

A method of fabricating a memory cell array by arranging a plurality of SRAM cells in rows and columns and connecting each SRAM cell of said array to a word line and to a pair of bit lines, wherein each of said SRAM cells is fabricated by: providing a semiconductor substrate; forming a P well in said semiconductor substrate; forming an N well in said semiconductor substrate; providing a flip-flop including two access transistors and a pair of cross coupled inverters, wherein each pair of cross-coupled inverters includes a pull up transistor defining a P type active region in said N well and a pull down transistor defining an N type active region in said P well; arranging an isolation region to isolate said N type active region from said P type active region; providing a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said pull down transistor and a P+ polysilicon layer forming a portion of said pull up transistor; forming a first silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein said first silicon rich barrier layer is arranged such that migration of N+ and P+dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich barrier layer; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein said second silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 65

A method of fabricating a computer system by arranging a microprocessor in communication with a memory cell array via a data communication path and fabricating said memory cell array by arranging a plurality of said SRAM cells in rows and columns and connecting each SRAM cell of said array to a word line and to a pair of bit lines, wherein each of said SRAM cells is fabricated by: providing a semiconductor substrate; forming a P well in said semiconductor substrate; forming an N well in said semiconductor substrate; providing a flip-flop including two access transistors and a pair of cross coupled inverters, wherein each pair of cross-coupled inverters includes a pull up transistor defining a P type active region in said N well and a pull down transistor defining an N type active region in said P well; arranging an isolation region to isolate said N type active region from said P type active region; providing a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said pull down transistor and a P+ polysilicon layer forming a portion of said pull up transistor; forming a first silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein said first silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich barrier layer; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein said second silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich barrier layer.

Claim 66

A method of fabricating a computer system by arranging a microprocessor in communication with a memory cell array via a data communication path and fabricating said memory cell array by arranging a plurality of said SRAM cells in rows and columns and connecting each SRAM cell of said array to a word line and to a pair of bit lines, wherein each of said SRAM cells is fabricated by: providing a semiconductor substrate; forming a P well in said semiconductor substrate; forming an N well in said semiconductor substrate; providing a flip-flop including two access transistors and a pair of cross coupled inverters, wherein each pair of cross-coupled inverters includes a pull up transistor defining a P type active region in said N well and a pull down transistor defining an N type active region in said P well; arranging an isolation region to isolate said N type active region from said P type active region; providing a polycilicide gate electrode structure composed of a polysilicon film and an overlying conductive layer, wherein said polysilicon film comprises an N+ polysilicon layer forming a portion of said pull down transistor and a P+ polysilicon layer forming a portion of said pull up transistor; forming a first silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure under a substantial portion of said polysilicon film between said polysilicon film and said semiconductor substrate, wherein said first silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said substrate is significantly impeded by said first silicon rich barrier layer; and forming a second silicon rich barrier layer comprising silicon and nitrogen in said polycilicide gate electrode structure over a substantial portion of said polysilicon film between said polysilicon film and said conductive layer, wherein said second silicon rich barrier layer is arranged such that migration of N+ and P+ dopants from said N+ and P+ polysilicon layers to said conductive layer is significantly impeded by said second silicon rich barrier layer.