US7042971B1
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Delay-locked loop with built-in self-test of phase margin
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2001-06-12
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Granted: 2006-05-09
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Expires: 2021-06-12
Abstract
Abstract A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.
Inventors
- 👤 Ian M. Flanagan
- 👤 Roger L. Roisen
- 👤 Dayanand K. Reddy
- 👤 Joel J. Christiansen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:41
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/095
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
76 words
A method of measuring phase margin of a delay-locked loop (DLL) having a reference input, the method comprising: (a) applying a reference clock to the reference input; (b) providing an auxiliary variable delay within the DLL; (c) varying the auxiliary variable delay until the DLL becomes unstable; and (d) generating a phase margin output related to the phase margin as a function of a value of the auxiliary variable delay at which the DLL becomes unstable.
Claim 2
Independent Claim
76 words
A method of measuring phase margin of a delay-locked loop (DLL) having a reference input, the method comprising: (a) applying a reference clock to the reference input; (b) providing an auxiliary variable delay within the DLL; (c) varying the auxiliary variable delay until the DLL becomes unstable; and (d) generating a phase margin output related to the phase margin as a function of a value of the auxiliary variable delay at which the DLL becomes unstable.
Claim 3
Dependent Claim
66 words
The method of claim 1 wherein: step (b) comprises providing an auxiliary delay line within a delay loop in the DLL, wherein the auxiliary delay line comprises a delay input, a delay output and a plurality of delay cells which are coupled together in series with the delay input; and step (c) comprises multiplexing outputs of respective ones of the delay cells to the delay output.
Claim 4
Dependent Claim
50 words
The method of claim 2 wherein step (c) further comprises: (c) (1) providing a counter having a count output; (c) (2) multiplexing the outputs of respective ones of the delay cells to the delay output based on the count output; and (c) (3) repetitively incrementing and decrementing the count output.
Claim 5
Dependent Claim
41 words
The method of claim 3 wherein step (d) comprises: (d) (1) generating a phase margin output related to the phase margin as a function of the count output at which the DLL switches between a phase-locked state and a phase-unlocked state.
Claim 6
Dependent Claim
63 words
The method of claim 4 wherein step (d) further comprises: (d) (2) generating a lock detect signal having a first logic state when the DLL is in the phase-locked state and a second, different logic state when DLL is in the phase-unlocked state; and (d) (3) latching the count output when the lock detect signal switches between the first and second logic states.
Claim 7
Dependent Claim
42 words
The method of claim 1 wherein: step (b) comprises providing an analog voltage-controlled delay element within the DLL, which has a control voltage input; and step (c) comprises applying a control voltage to the control voltage input and varying the control voltage.
Claim 8
Dependent Claim
26 words
The method of claim 6 wherein varying the control voltage comprises varying the control voltage such that the control voltage forms a triangular waveform over time.
Claim 9
Dependent Claim
72 words
The method of claim 7 wherein the generating step (d) comprises: (d) (1) generating a lock detect signal having a first logic state when the DLL is in a phase-locked state and a second, different logic state when DLL is in a phase-unlocked state; and (d) (2) generating the phase margin output as a function of a duty cycle of the lock detect signal as the control voltage is varied over time.
Claim 10
Dependent Claim
62 words
The method of claim 8 wherein step (d)(2) comprises: (d) (2) (i) low-pass filtering the lock detect signal to produce a filtered lock detect signal having a DC voltage; (d) (2) (ii) comparing the DC voltage with a reference voltage level to produce a comparison output; and (d) (2) (iii) generating the phase margin output as a function of the comparison output.
Claim 11
Dependent Claim
74 words
The method of claim 1 wherein the DLL is embedded within an integrated circuit and wherein the method further comprises: (e) activating a built-in self-test state machine which is embedded within the integrated circuit and adapted to perform step (c); and (f) reading the phase margin output with the built-in self-test state machine and generating a self-test output from the state machine that represents functionality of the DLL based on the phase margin output.
Claim 12
Dependent Claim
152 words
A delay-locked loop (DLL) comprising: a reference input; a feedback input; a DLL output which is coupled to the feedback input; a phase detector coupled to the reference input and the feedback input and having a phase control output; a charge pump coupled to the phase control output; a loop filter coupled to an output of the charge pump; a main variable delay element coupled between the reference input and the DLL output and having a first control input coupled to the loop filter; an auxiliary variable delay element coupled in series with the main variable delay element, between the reference input and the feedback input, and having a second control input and an auxiliary delay that is variable to a critical delay at which the DLL becomes unstable; and a phase margin measurement circuit which generates a phase margin output based on the critical delay at which the DLL becomes unstable.
Claim 13
Dependent Claim
152 words
A delay-locked loop (DLL) comprising: a reference input; a feedback input; a DLL output which is coupled to the feedback input; a phase detector coupled to the reference input and the feedback input and having a phase control output; a charge pump coupled to the phase control output; a loop filter coupled to an output of the charge pump; a main variable delay element coupled between the reference input and the DLL output and having a first control input coupled to the loop filter; an auxiliary variable delay element coupled in series with the main variable delay element, between the reference input and the feedback input, and having a second control input and an auxiliary delay that is variable to a critical delay at which the DLL becomes unstable; and a phase margin measurement circuit which generates a phase margin output based on the critical delay at which the DLL becomes unstable.
Claim 14
Dependent Claim
69 words
The DLL of claim 11 wherein the auxiliary variable delay element comprises: an auxiliary delay input; an auxiliary delay output; a plurality of delay cells coupled together in series with the auxiliary delay input; and a multiplexer comprising a plurality of multiplexer data inputs coupled to respective outputs of the plurality of delay cells, a multiplexer data output coupled to the auxiliary delay output and a select control input.
Claim 15
Dependent Claim
45 words
The DLL of claim 12 wherein the phase margin measurement circuit comprises: a counter having a count output coupled to the select control input; and an output latch having a latch input coupled to the count output, a latch output, and a latch control input.
Claim 16
Dependent Claim
74 words
The DLL of claim 13 wherein the phase margin measurement circuit further comprises: a lock detect circuit having clock inputs, which are coupled to respective ones of the reference input and the feedback input, and a lock output coupled to the latch control input, wherein the lock output has a first logic state when the DLL is in a phase-locked state and a second, different logic state when DLL is in a phase-unlocked state.
Claim 17
Dependent Claim
38 words
The DLL of claim 11 wherein the auxiliary variable delay element comprises: an analog voltage-controlled delay element having a control voltage input; and a control voltage generator having a control voltage output coupled to the control voltage input.
Claim 18
Dependent Claim
26 words
The DLL of claim 15 wherein the control voltage generator generates a control voltage on the control voltage output that has a triangular waveform over time.
Claim 19
Dependent Claim
116 words
The DLL of claim 16 wherein the phase margin measurement circuit comprises comprises: a lock detect circuit having clock inputs which are coupled to respective ones of the reference input and the feedback input and a lock output which has a first logic state when the DLL is in a phase-locked state and a second, different logic state when DLL is in a phase-unlocked state; a low-pass filter having a filter input coupled to the lock output and having a filter output; and a comparator having a first comparator input coupled to the filter output, a second comparator input coupled to the a reference voltage and a comparator output, which is indicative of the phase margin.
Claim 20
Dependent Claim
129 words
A delay-locked loop (DLL) comprising: a reference input for receiving a reference signal; a feedback input for receiving a feedback signal; a DLL output coupled to the feedback input; first variable delay means coupled between the reference input and the DLL output for providing a first variable delay; phase control means for detecting a phase difference between the reference signal and the feedback signal and for varying the first variable delay as a function of the phase difference; and phase margin measurement means for adding further delay in series with the first variable delay means, between the reference input and the feedback input, and for generating a phase margin output as a function of an amount of the further delay that is required for the DLL to become unstable.
Claim 21
Dependent Claim
129 words
A delay-locked loop (DLL) comprising: a reference input for receiving a reference signal; a feedback input for receiving a feedback signal; a DLL output coupled to the feedback input; first variable delay means coupled between the reference input and the DLL output for providing a first variable delay; phase control means for detecting a phase difference between the reference signal and the feedback signal and for varying the first variable delay as a function of the phase difference; and phase margin measurement means for adding further delay in series with the first variable delay means, between the reference input and the feedback input, and for generating a phase margin output as a function of an amount of the further delay that is required for the DLL to become unstable.
References Cited (Backward Citations)
US5828250A
Cited
US5963069A
Cited
US6173432B1
Cited
US6392456B1
Cited
US6212127B1
Cited
US6262634B1
Cited
US6868504B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2009-05-08 | 2009-11-07 | 2010-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-05-08 | 2013-11-07 | 2014-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-05-08 | 2017-11-07 | 2018-05-09 | $7700.00 | Window Closed / Lapsed |