Serial data interface

Claim 3

The method of claim 1 , wherein the step of interrupting occurs in response to an external interruption signal received by the integrated circuit.

Claim 4

The method of claim 2 , further comprising the step of receiving the interruption signal on another one of the input/outputs associated with the operation of the integrated circuit.

Claim 5

The method of claim 2 , wherein the step of transmitting/receiving serial data comprises synchronous transmission/reception of serial data from/to the integrated circuit on the at least one input/output.

Claim 6

The method of claim 4 , and further comprising the step of receiving a separate serial clock on another one of the input/outputs associated with the operation of the integrated circuit.

Claim 7

The method of claim 5 , wherein the function of the integrated circuit associated with the other one of the inputs/outputs is overridden in the presence of reception of the serial clock.

Claim 8

The method of claim 5 , wherein the step of interrupting is initiated in response to the reception of the serial clock.

Claim 9

The method of claim 5 , wherein the integrated circuit has a plurality of input/output pins, a first of the input/output pins associated with the at least one input/output and a second of the input/output pins associated with the other of the inputs/outputs.

Claim 10

The method of claim 8 and further comprising the step of multiplexing the operation of the first of the input/output pins to receive/transmit, in a normal mode of operation, data associated with the operation of the integrated circuit and, in a second serial data mode, to receive/transmit serial data over the first of the input/output pins.

Claim 11

The method of claim 9 and further comprising the steps of: providing a plurality of registers; addressing one of the plurality of registers; and storing received serial data in the addressed one of the plurality of registers or extracting information from the addressed one of the plurality of registers and transmitting the extracted information as serial data.

Claim 12

The method of claim 10 and further comprising the step of interfacing the registers with the operation of the integrated circuit when uninterrupted.

Claim 15

The method of claim 12 , wherein the at least another one input/outputs has a second predefined function associated with the operation of the integrated circuit, and further comprising the step of interrupting at least the second predefined function on the at least another one of the input/outputs in response to the step of receiving the serial clock signal.

Claim 16

The method of claim 13 , wherein the step of interrupting occurs prior to the step of transmitting/receiving.

Claim 17

The method of claim 13 , wherein the first predefined function of the integrated circuit associated with the one input/output is overidden in the presence of reception of the serial clock.

Claim 18

The method of claim 13 , wherein the integrated circuit has a plurality of input/output pins, a first of the input/output pins associated with the one input/output and a second of the input/output pins associated with the at least another one of the inputs/outputs.

Claim 19

The method of claim 16 and further comprising the step of multiplexing the operation of the second of the input/output pins to transmit or receive, in a normal mode of operation, data associated with the operation of the integrated circuit and, in a second serial data mode, to receive and transmit serial data over the second of the input/output pins.

Claim 20

The method of claim 17 , and further comprising the steps of: providing a plurality of registers; addressing one of the plurality of registers; and storing received serial data in the addressed one of the plurality of registers or extracting information from the addressed one of the plurality of registers and transmitting the extracted information as serial data.

Claim 21

The method of claim 18 and further comprising the step of interfacing the registers with the operation of the integrated circuit when uninterrupted.

Claim 22

An integrated circuit with a serial communication interface, comprising: interruption circuitry for interrupting a normal operation of the integrated circuit on at least one input/output associated with the operation of the integrated circuit, which normal operation does not include a function of transmitting/receiving serial data; and a transceiver for transmitting/receiving serial data over said at least one input/output, the operation of which was interrupted, and during the interruption thereof.

Claim 23

An integrated circuit with a serial communication interface, comprising: interruption circuitry for interrupting a normal operation of the integrated circuit on at least one input/output associated with the operation of the integrated circuit, which normal operation does not include a function of transmitting/receiving serial data; and a transceiver for transmitting/receiving serial data over said at least one input/output, the operation of which was interrupted, and during the interruption thereof.

Claim 24

The integrated circuit of claim 20 , wherein said interruption circuitry interrupts the operation of the integrated circuit on said at least one input/output in response to an external interruption signal received by the integrated circuit.

Claim 25

The integrated circuit of claim 21 , and further comprising said interruption circuitry is operable to receive the interruption signal on another one of the input/outputs associated with the operation of the integrated circuit.

Claim 26

The integrated circuit of claim 22 , said transceiver transmits/receives serial data as a synchronous transmission/reception of serial data from/to the integrated circuit on the at least one input/output.

Claim 27

The integrated circuit of claim 23 , wherein said interruption circuitry includes serial clock circuitry for receiving a separate serial clock on another one of the input/outputs associated with the operation of the integrated circuit, the reception of said serial clock comprising said external interruption signal.

Claim 28

The integrated circuit of claim 24 , wherein the function of the integrated circuit associated with the other one of the inputs/outputs is overridden in the presence of reception of said serial clock.

Claim 29

The integrated circuit of claim 24 , wherein said interruption circuitry is operable to interrupt in response to the reception of said serial clock.

Claim 30

The integrated circuit of claim 24 , wherein the integrated circuit has a plurality of input/output pins, a first of the input/output pins associated with said at least one input/output and a second of said input/output pins associated with said other of the inputs/outputs.

Claim 31

The integrated circuit of claim 27 and further comprising a multiplexer for multiplexing the operation of said first of the input/output pins to receive/transmit, in a normal mode of operation, data associated with the operation of the integrated circuit and, in a second serial data mode, to receive/transmit serial data over said first of the input/output pins.

Claim 32

The integrated circuit of claim 28 and further comprising: a plurality of registers; address circuitry for addressing one of said plurality of registers; and an register control for storing received serial data in the addressed one of said plurality of registers or extracting information from the addressed one of said plurality of registers and transmitting the extracted information as serial data.

Claim 33

The integrated circuit of claim 29 and further comprising an interface device for interfacing the registers with the operation of the integrated circuit when uninterrupted.

Claim 34

A integrated circuit with a serial communication interface, comprising: a serial clock interface for receiving a serial clock signal on one input/output associated with an operation of the integrated circuit, which said one input/output has a first predefined function associated with the operation of the integrated circuit, which first predefined function associated with said one input/output does not include a timing operation associated with transmitting/receiving serial data; and a transceiver for transmitting/receiving serial data over at least another one of the input/outputs associated with the operation of the integrated circuit after receipt of said serial clock on said one input/output, the operation of said transceiver is synchronized with said received serial clock.

Claim 35

A integrated circuit with a serial communication interface, comprising: a serial clock interface for receiving a serial clock signal on one input/output associated with an operation of the integrated circuit, which said one input/output has a first predefined function associated with the operation of the integrated circuit, which first predefined function associated with said one input/output does not include a timing operation associated with transmitting/receiving serial data; and a transceiver for transmitting/receiving serial data over at least another one of the input/outputs associated with the operation of the integrated circuit after receipt of said serial clock on said one input/output, the operation of said transceiver is synchronized with said received serial clock.

Claim 36

The integrated circuit of claim 31 , wherein the at least another one input/outputs has a second predefined function associated with the operation of the integrated circuit, and further comprising an interruption circuit for interrupting at least said second predefined function on said at least another one of the input/outputs in response to receiving said serial clock.

Claim 37

The integrated circuit of claim 32 , wherein the interruption operation of said interruption circuit occurs prior to said transceiver being enabled for transmitting/receiving.

Claim 38

The integrated circuit of claim 32 , wherein said first predefined function of the integrated circuit associated with said one input/output is overidden in the presence of reception of the serial clock by said serial clock interface.

Claim 39

The integrated circuit of claim 32 , wherein the integrated circuit has a plurality of input/output pins, a first of said input/output pins associated with said one input/output and a second of said input/output pins associated with said at least another one of the inputs/outputs.

Claim 40

The integrated circuit of claim 35 and further comprising a multiplexor for multiplexing the operation of said second of said input/output pins to transmit or receive, in a normal mode of operation, data associated with the operation of the integrated circuit and, in a second serial data mode, to receive and transmit serial data over said second of said input/output pins.

Claim 41

The integrated circuit of claim 36 , and further comprising: a plurality of registers; addressing circuitry for addressing one of said plurality of registers; and a register control for storing received serial data in the addressed one of said plurality of registers or extracting information from the addressed one of said plurality of registers and transmitting the extracted information as serial data.

Claim 42

The integrated circuit of claim 37 and further comprising an interface for interfacing said registers with the operation of the integrated circuit when uninterrupted.