US6963613B2 — Method of communicating between modules in a deco…

Claim 1

Independent Claim 182 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and adapted to issue commands to an entropy decoding accelerator; and an entropy decoding accelerator adapted to receive commands from the core decoder processor and to perform entropy decoding operations on entropy-coded code in the data stream in response to said commands, wherein the entropy decoding accelerator is adapted to provide a command status signal to the core decoder processor, the command status signal indicating whether or not a command is completed; wherein the core decoder processor is adapted to issue a register-read instruction to the entropy decoding accelerator that causes the contents of a register in the entropy decoding accelerator to be provided to the core decoder processor, wherein if the command status signal indicates that a previous command is not yet completed when a register-read instruction is issued by the core decoder processor, the contents of the register in the entropy decoder are not provided to the core decoder processor until the command status signal indicates that the previous command is completed.

Claim 2

Dependent Claim 182 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and adapted to issue commands to an entropy decoding accelerator; and an entropy decoding accelerator adapted to receive commands from the core decoder processor and to perform entropy decoding operations on entropy-coded code in the data stream in response to said commands, wherein the entropy decoding accelerator is adapted to provide a command status signal to the core decoder processor, the command status signal indicating whether or not a command is completed; wherein the core decoder processor is adapted to issue a register-read instruction to the entropy decoding accelerator that causes the contents of a register in the entropy decoding accelerator to be provided to the core decoder processor, wherein if the command status signal indicates that a previous command is not yet completed when a register-read instruction is issued by the core decoder processor, the contents of the register in the entropy decoder are not provided to the core decoder processor until the command status signal indicates that the previous command is completed.

Claim 3

Dependent Claim 45 words

The system of claim 1 wherein the entropy decoding accelerator comprises a command status register that indicates whether or not a command is completed and wherein the core decoder processor is adapted to poll the command status register to determine if the command is completed.

Claim 4

Dependent Claim 33 words

The system of claim 2 wherein the core decoder processor does not issue a new command to the entropy decoder accelerator unless the command status register indicates that a previous command is completed.

Claim 5

Dependent Claim 119 words

The system of claim 1 wherein the register-read instruction includes a wait bit, wherein if the wait bit is set and the command status signal indicates that a previous command is not yet completed when a register-read instruction is issued by the core decoder processor, the contents of the register in the entropy decoder are not provided to the core decoder processor until the command status signal indicates that the previous command is completed, but wherein if the wait bit is not set and a register-read instruction is issued by the core decoder processor, the contents of the register in the entropy decoder are provided to the core decoder processor regardless of the value of the command status signal.

Claim 6

Dependent Claim 42 words

The system of claim 1 wherein the core decoder processor is adapted to perform decoding functions on a coded media data stream and the entropy decoding accelerator is adapted to perform entropy decoding operations on entropy-coded code in the media data stream.

Claim 7

Dependent Claim 42 words

The system of claim 1 wherein the core decoder processor is adapted to perform decoding functions on a coded video data stream and the entropy decoding accelerator is adapted to perform entropy decoding operations on entropy-coded code in the video data stream.

Claim 8

Dependent Claim 34 words

The decoding system of claim 1 wherein the entropy decoding accelerator is a variable-length decoding accelerator adapted to perform variable-length decoding operations on variable-length code in the data stream in response to said commands.

Claim 9

Dependent Claim 30 words

The decoding system of claim 1 wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on single-syntax elements in the data stream in response to said commands.

Claim 10

Dependent Claim 33 words

The decoding system of claim 1 wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on complete blocks of syntax elements in the data stream in response to said commands.

Claim 11

Dependent Claim 37 words

The decoding system of claim 9 wherein the entropy decoding accelerator is adapted to concurrently perform entropy decoding operations on single-syntax elements and complete blocks of single-syntax elements in the data stream in response to said commands.

Claim 12

Dependent Claim 37 words

The decoding system of claim 1 wherein the entropy decoding accelerator is adapted to perform entropy decoding operations on single-syntax elements and on complete blocks of syntax elements in the data stream in response to said commands.

Claim 13

Independent Claim 103 words

A method of controlling first and second decoding accelerators coupled to a core decoder processor adapted to decode a data stream, the first and second accelerators adapted to assist the core decoder processor with first and second decoding functions respectively, the method comprising: (a) providing, with the core decoder processor, first and second commands to the first and second accelerators respectively via posted write operations; and (b) polling the first and second accelerators with the core decoder processor to determine whether first and second operations, corresponding to the first and second commands respectively, have been performed by the first and second accelerators respectively.

Claim 14

Independent Claim 103 words

A method of controlling first and second decoding accelerators coupled to a core decoder processor adapted to decode a data stream, the first and second accelerators adapted to assist the core decoder processor with first and second decoding functions respectively, the method comprising: (a) providing, with the core decoder processor, first and second commands to the first and second accelerators respectively via posted write operations; and (b) polling the first and second accelerators with the core decoder processor to determine whether first and second operations, corresponding to the first and second commands respectively, have been performed by the first and second accelerators respectively.

Claim 15

Dependent Claim 54 words

The method of claim 12 wherein the first and second commands instruct the first and second accelerators to perform the first and second decoding functions and wherein polling step (b) comprises polling the first and second accelerators with the core decoder processor to determine whether the first and second decoding functions have been completed.

Claim 16

Dependent Claim 32 words

The method of claim 12 further comprising a step (c), performed after providing step (a) and prior to polling step (b), of performing a third decoding function with the core decoder processor.

Claim 17

Dependent Claim 49 words

The method of claim 12 wherein providing step (a) comprises: (a)(i) providing the first and second commands to an intermediate storage element; and (a)(ii) writing the first and second commands to the first and second accelerators when both the first and second accelerators are ready to receive the commands.

Claim 18

Dependent Claim 22 words

The method of claim 15 wherein step (a)(ii) is performed a plurality of core decoder clock cycles after step (a)(i) is performed.

Claim 19

Dependent Claim 64 words

The method of claim 12 further comprising a step (c), after step (b), of: (c) after the core decoder processor determines, via its polling of the first and second accelerators, that the operations corresponding to the first and second commands have been performed, providing, with the core decoder processor, third and fourth commands to the first and second accelerators, respectively, via posted write operations.

Claim 20

Dependent Claim 66 words

The method of claim 12 further comprising a step (c), after step (b), of: (c) after the core decoder processor determines, via its polling of the first and second accelerators, that the first and second operations have been performed by the first and second accelerators, providing, with the core decoder processor, third and fourth commands to the first and second accelerators respectively, via posted write operations.

Claim 21

Dependent Claim 31 words

The method of claim 18 wherein the second decoding function, performed by the second accelerator, depends on a product previously produced by the first decoding function, performed by the first accelerator.

Claim 22

Dependent Claim 153 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; and a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the first decoding accelerator is adapted to provide status data indicative of a status of the first accelerator to the co-processor status register; and a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register; wherein each of the first and second decoding accelerators are assumed a set of bit positions in the co-processor status register.

Claim 23

Dependent Claim 153 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; and a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the first decoding accelerator is adapted to provide status data indicative of a status of the first accelerator to the co-processor status register; and a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register; wherein each of the first and second decoding accelerators are assumed a set of bit positions in the co-processor status register.

Claim 24

Dependent Claim 48 words

The system of claim 20 wherein the core decoder processor is adapted to issue commands to the first and second decoding accelerators and wherein the first and second decoding accelerators are adapted to provide status data indicative of whether a command is completed to the co-processor status register.

Claim 25

Dependent Claim 47 words

The system of claim 20 further comprising: a third decoding accelerator adapted to assist the core decoder processor with a third decoding function, wherein the third decoding accelerator is adapted to provide status data indicative of a status of the third accelerator to the co-processor status register.

Claim 26

Dependent Claim 79 words

The system of claim 20 further comprising: a data bus coupled to the co-processor interface and to the first and second decoding accelerators, wherein each of the first and second accelerators are adapted to provide status data to the bit positions of the data bus that correspond to the bit positions assigned each accelerator in the co-processor status register, and wherein the co-processor interface is adapted to read the contents of the data bus into the co-processor status register.

Claim 27

Dependent Claim 133 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; an entropy decoding accelerator adapted to perform entropy decoding operations on entropy-coded code in the data stream and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status register; and a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register.

Claim 28

Dependent Claim 133 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; an entropy decoding accelerator adapted to perform entropy decoding operations on entropy-coded code in the data stream and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status register; and a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register.

Claim 29

Dependent Claim 158 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status register; and a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register, wherein the second decoding accelerator comprises one of an inverse quantizer, an inverse transform module, a pixel filter, a motion compensation module and a deblocking filter.

Claim 30

Dependent Claim 158 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status register; and a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register, wherein the second decoding accelerator comprises one of an inverse quantizer, an inverse transform module, a pixel filter, a motion compensation module and a deblocking filter.

Claim 31

Dependent Claim 153 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status resister; and a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register and wherein the second decoding accelerator is coupled to the core decoder processor via an interface other than the co-processor interface.

Claim 32

Dependent Claim 153 words

A decoding system comprising: a core decoder processor adapted to perform decoding functions on a coded data stream and having a co-processor interface, the co-processor interface including a co-processor status register adapted to receive a status of a co-processor; a first decoding accelerator adapted to assist the core decoder processor with a first decoding function and coupled to the core decoder processor via the co-processor interface, wherein the entropy decoding accelerator is adapted to provide status data indicative of a status of the entropy decoding accelerator to the co-processor status resister; and a second decoding accelerator adapted to assist the core decoder processor with a second decoding function, wherein the second decoding accelerator is adapted to provide status data indicative of a status of the second accelerator to the co-processor status register and wherein the second decoding accelerator is coupled to the core decoder processor via an interface other than the co-processor interface.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2008-11-07	2009-05-09	2009-11-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2012-11-07	2013-05-09	2013-11-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2016-11-07	2017-05-09	2017-11-08	$7700.00	Window Closed / Lapsed

Method of communicating between modules in a decoding system

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