Delay model circuit for use in delay locked loop

Claim 1

A delay model circuit for providing a negative delay to a delay locked loop (DLL) of a semiconductor device, comprising: a first delay circuit for providing a first delay amount; a second delay circuit having N number of delay load blocks, each having a different load delay amount from others, N being a positive integer; an adjustable load control circuit for generating an adjustable load control signal, wherein the adjustable load control circuit includes an input port for receiving an adjustable test mode signal having M number of bits, M being a positive integer; and a decoding circuit for generating the adjustable load control signal having N number of bits by decoding the adjustable test mode signal, each bit employed in controlling each electrically controllable switch device; and a switching circuit for selectively coupling at least one delay load block to the first delay circuit in response to the adjustable load control signal to thereby allow the delay model circuit to provide the negative delay as a combination of the first delay amount and a second delay amount provided by the selected delay load block.