Current starved DAC-controlled delay locked loop

Claim 2

A delay lock loop circuit comprising: a reference clock input signal; a delay line output; a divider circuit coupled to said reference clock input; a phase detector configured to receive signals from said delay line output and said divider, said phase detector configured to generate a phase signal; a control logic configured to receive compare outputs from said phase detector; a means for implementing a binary search of said compare outputs from said control logic for generating a calibration bit, said means configured to lock a delay loop after a set number of comparisons; and a means for applying the calibration bit to a transmission on an output line.

Claim 3

The circuit of claim 1 , wherein said means for implementing a binary search includes a control logic register and a shift register.

Claim 4

The circuit of claim 2 , wherein said control logic register is a 5 bit register.

Claim 5

The circuit of claim 3 , wherein the shift register is a 6 bit register.

Claim 6

The circuit of claim 1 , wherein the divider circuit divides said reference clock input signal such that timing of said reference clock input signal sent to the control logic is sent after generation of the calibration bit from any previous input.

Claim 7

The circuit of claim 1 , wherein said delay line output is sent to an analog delay locked loop circuit.

Claim 8

The circuit of claim 1 , wherein said divider circuit divides by 8.

Claim 9

The circuit of claim 1 , wherein said means for generating the calibration bit is an adder circuit.

Claim 10

A delay lock loop circuit comprising: a reference clock input signal; a delay line output; a divider circuit coupled to said reference clock input; a phase detector configured to receive signals from said delay line output and said divider, said phase detector configured to generate a phase signal; a control logic configured to receive compare outputs from said phase detector; a control logic register; a shift register; said control logic register and shift register being configured to implement a binary search of compare outputs from said control logic and generate a calibration bit, said shift register being configured to implement a binary search to lock a delay loop after a set number of comparisons; and an adder for applying the calibration bit to a transmission on an output line.

Claim 11

A delay lock loop circuit comprising: a reference clock input signal; a delay line output; a divider circuit coupled to said reference clock input; a phase detector configured to receive signals from said delay line output and said divider, said phase detector configured to generate a phase signal; a control logic configured to receive compare outputs from said phase detector; a control logic register; a shift register; said control logic register and shift register being configured to implement a binary search of compare outputs from said control logic and generate a calibration bit, said shift register being configured to implement a binary search to lock a delay loop after a set number of comparisons; and an adder for applying the calibration bit to a transmission on an output line.

Claim 12

The circuit of claim 9 , wherein said control logic register is a 5 bit register.

Claim 13

The circuit of claim 9 , wherein said shift register is a 6 bit register.

Claim 14

The circuit of claim 9 , wherein the divider divides said reference clock input signal such that timing of said reference clock input signal sent to the control logic is sent after generation of the calibration bit from any previous input.

Claim 15

The circuit of claim 9 , wherein said delay line output is sent to an analog delay locked loop circuit.

Claim 16

The circuit of claim 9 , wherein said divider circuit divides by 8.