US6239633B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital DLL circuit
Assignee: Longitude Licensing Ltd
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Filing: 1999-10-07
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Granted: 2001-05-29
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Expires: 2019-10-07
Abstract
Abstract A digital Delay-Locked Loop (DLL) circuit includes a phase locking unit, an adder, and a phase delay unit. The phase locking unit generates a first internal clock phase-locked with an external clock by adjusting a first digital phase control amount on the basis of a phase difference between an external clock and the first internal clock. The adder adds a predetermined phase control amount to the first digital phase control amount to output a second digital phase control amount when the first internal clock is generated by the phase locking unit. The phase delay unit generates a second internal clock delayed from the external clock by the predetermined control amount, on the basis of the second digital phase control amount from the adder.
Inventors
- 👤 Kazutaka Miyano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:13
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G11C7/22; G11C7/222; H03L7/07; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
116 words
A digital Delay-Locked Loop (DLL) circuit comprising: phase locking means for generating a first internal clock phase-locked with an external clock by adjusting a first digital phase control amount on the basis of a phase difference between an external clock and the first internal clock; addition means for adding a predetermined phase control amount to the first digital phase control amount to output a second digital phase control amount when the first internal clock is generated by said phase locking means; and phase delay means for generating a second internal clock delayed from the external clock by the predetermined phase control amount, on the basis of the second digital phase control amount from said addition means.
Claim 2
Dependent Claim
116 words
A digital Delay-Locked Loop (DLL) circuit comprising: phase locking means for generating a first internal clock phase-locked with an external clock by adjusting a first digital phase control amount on the basis of a phase difference between an external clock and the first internal clock; addition means for adding a predetermined phase control amount to the first digital phase control amount to output a second digital phase control amount when the first internal clock is generated by said phase locking means; and phase delay means for generating a second internal clock delayed from the external clock by the predetermined phase control amount, on the basis of the second digital phase control amount from said addition means.
Claim 3
Dependent Claim
26 words
A circuit according to claim 1 , wherein said phase locking means generates a first internal clock absolute phase-locked with the external clock without any delay.
Claim 4
Dependent Claim
129 words
A circuit according to claim 1 , wherein said phase locking means comprises: phase determination means for comparing a phase of the external clock with that of the first internal clock to output a phase determination signal; phase amount output means for outputting the first digital phase control amount to said addition means on the basis of the phase determination signal from said phase determination means; and first clock mixing means for receiving a plurality of frequency-divided clocks having a phase difference of a predetermined phase, generating from the plurality of frequency-divided clocks, on the basis of the first digital phase control amount from said phase amount output means, a first internal clock phase-locked with the external clock, and outputting the first internal clock to said phase determination means.
Claim 5
Dependent Claim
55 words
A circuit according to claim 3 , wherein said phase delay means comprises second clock mixing means for receiving the plurality of frequency-divided clocks, and generating from the plurality of frequency-divided clocks, on the basis of the second digital phase control amount from said addition means, a second internal clock phase-locked with the external clock.
Claim 6
Dependent Claim
79 words
A circuit according to claim 4 , wherein the first and second digital phase delay amounts are made up of a clock selection signal and phase signal comprised of a plurality of signal bits, and said first and second clock mixing means selects two of the plurality of frequency-divided clocks in accordance with the clock selection signal and respectively generate first and second internal clocks having phases between the two selected frequency-divided clocks in accordance with the phase signal.
Claim 7
Dependent Claim
36 words
A circuit according to claim 5 , wherein the first and second digital phase control amounts are made up of the clock selection signal of upper two bits and the phase signal of remaining six bits.
Claim 8
Dependent Claim
44 words
A circuit according to claim 4 , further comprising frequency-dividing means for outputting to said first and second clock mixing means the plurality of frequency-divided clocks having a phase difference of a predetermined phase, the frequency-divided clocks being obtained by frequency-dividing the external clock.
References Cited (Backward Citations)
US5883534A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-28 | 2004-11-27 | 2005-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-28 | 2008-11-27 | 2009-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-28 | 2012-11-27 | 2013-05-29 | $7700.00 | Window Closed / Lapsed |