US6917660B2
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US
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Adaptive de-skew clock generation
Assignee: Intel Corp
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Filing: 2001-06-04
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Granted: 2005-07-12
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Expires: 2021-06-04
Abstract
Abstract A signal delay circuit that compensates for other delays introduced within the signal delay circuit itself. A delay-locked loop may produce multiple delayed clock signals, each having a defined phase difference with respect to, and representing a different delay from, a reference clock. A synchronization circuit may determine a first selection value that selects a first delayed clock whose delay compensates for the propagation delays created in a selection circuit. A selection circuit may add a specified offset value to the first selection value to produce a second selection value, and use the second selection value to select a second delayed clock whose delay approximates the sum of the internal delay of the selection circuit and the delay specified by the offset value.
Inventors
- 👤 Hongjiang Song
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:21
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H03K; H03K5/00; H03K5/15; H03K5/15013; H03L7/07; H03L7/081; H03L7/0812; H03L7/0814; H04; H04L; H04L7/00; H04L7/0016; H04L7/0033; H04L7/0037; H03L7/0816; H04L7/0008
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
106 words
An apparatus, comprising: a multiple-clock delay circuit to receive a reference clock signal and to provide multiple delayed output clock signals; a selection circuit to receive an offset value and to receive the multiple delayed output clock signals, the selection circuit including an output circuit having an output load to output data timed with a first selected one of the multiple delayed output clock signals; and a synchronization circuit coupled to the multiple-clock delay circuit and the selection circuit and having a load simulation circuit to simulate the output load, the synchronization circuit to receive the reference clock signal and the multiple delayed output clock signals.
Claim 2
Independent Claim
106 words
An apparatus, comprising: a multiple-clock delay circuit to receive a reference clock signal and to provide multiple delayed output clock signals; a selection circuit to receive an offset value and to receive the multiple delayed output clock signals, the selection circuit including an output circuit having an output load to output data timed with a first selected one of the multiple delayed output clock signals; and a synchronization circuit coupled to the multiple-clock delay circuit and the selection circuit and having a load simulation circuit to simulate the output load, the synchronization circuit to receive the reference clock signal and the multiple delayed output clock signals.
Claim 3
Dependent Claim
16 words
The apparatus of claim 1 , wherein: the multiple-clock delay circuit includes a delay-locked loop circuit.
Claim 4
Dependent Claim
37 words
The apparatus of claim 1 , wherein: the synchronization circuit includes a first multiplexer to select a second selected one of the multiple delayed output clock signals to synchronize an intermediate clock signal with the reference signal.
Claim 5
Dependent Claim
33 words
The apparatus of claim 3 , wherein: the synchronization circuit includes a phase detector coupled to the multiplexer to detect a phase relationship between the reference clock signal and the intermediate clock signal.
Claim 6
Dependent Claim
23 words
The apparatus of claim 4 , wherein: the synchronization circuit includes an up/down counter coupled to the phase detector and the first multiplexer.
Claim 7
Dependent Claim
30 words
The apparatus of claim 1 , wherein: the selection circuit includes an adder circuit to add the first selection value to an offset value to produce a second selection value.
Claim 8
Dependent Claim
35 words
The apparatus of claim 6 , wherein: the selection circuit includes a second multiplexer coupled to the adder circuit to select a second one of the delayed output clock signals with the second selection value.
Claim 9
Independent Claim
133 words
A system, comprising: a processor; a synchronous dynamic random access memory; and a clock delay control circuit coupled to the processor and the memory, the clock delay control circuit including: a multiple-clock delay circuit to receive a reference clock signal and to provide multiple delayed output clock signals; a selection circuit to receive an offset value and to receive the multiple delayed output clock signals, the selection circuit including an output circuit having an output load to output data timed with a first selected one of the multiple delayed output clock signals; and a synchronization circuit coupled to the multiple-clock delay circuit and the selection circuit and having a load simulation circuit to simulate the output load, the synchronization circuit to receive the reference clock signal and the multiple delayed output clock signals.
Claim 10
Independent Claim
133 words
A system, comprising: a processor; a synchronous dynamic random access memory; and a clock delay control circuit coupled to the processor and the memory, the clock delay control circuit including: a multiple-clock delay circuit to receive a reference clock signal and to provide multiple delayed output clock signals; a selection circuit to receive an offset value and to receive the multiple delayed output clock signals, the selection circuit including an output circuit having an output load to output data timed with a first selected one of the multiple delayed output clock signals; and a synchronization circuit coupled to the multiple-clock delay circuit and the selection circuit and having a load simulation circuit to simulate the output load, the synchronization circuit to receive the reference clock signal and the multiple delayed output clock signals.
Claim 11
Dependent Claim
16 words
The system of claim 8 , wherein: the multiple-clock delay circuit includes a delay-locked loop circuit.
Claim 12
Dependent Claim
37 words
The system of claim 8 , wherein: the synchronization circuit includes a first multiplexer to select a second selected one of the multiple delayed output clock signals to synchronize an intermediate clock signal with the reference signal.
Claim 13
Dependent Claim
33 words
The system of claim 10 , wherein: the synchronization circuit includes a phase detector coupled to the multiplexer to detect a phase relationship between the reference clock signal and the intermediate clock signal.
Claim 14
Dependent Claim
23 words
The system of claim 11 , wherein: the synchronization circuit includes an up/down counter coupled to the phase detector and the first multiplexer.
Claim 15
Dependent Claim
30 words
The system of claim 8 , wherein: the selection circuit includes an adder circuit to add the first selection value to an offset value to produce a second selection value.
Claim 16
Dependent Claim
35 words
The system of claim 13 , wherein: the selection circuit includes a second multiplexer coupled to the adder circuit to select a second one of the delayed output clock signals with the second selection value.
Claim 17
Independent Claim
94 words
A method, comprising: providing multiple delayed clock signals; producing an intermediate clock from an output simulation circuit that simulates at least one characteristic of an output circuit; determining a selection value that selects one of the delayed clock signals to synchronize the intermediate clock with a reference clock; and adding an offset value to the selection value to select another of the delayed clock signals to provide an output signal from the output circuit, a phase of the output signal being delayed from the intermediate clock by an amount specified by the offset value.
Claim 18
Independent Claim
94 words
A method, comprising: providing multiple delayed clock signals; producing an intermediate clock from an output simulation circuit that simulates at least one characteristic of an output circuit; determining a selection value that selects one of the delayed clock signals to synchronize the intermediate clock with a reference clock; and adding an offset value to the selection value to select another of the delayed clock signals to provide an output signal from the output circuit, a phase of the output signal being delayed from the intermediate clock by an amount specified by the offset value.
Claim 19
Dependent Claim
29 words
The method of claim 15 , wherein: determining a selection value includes using a phase detector to determine a phase relationship between the intermediate clock and the reference clock.
Claim 20
Dependent Claim
25 words
The method of claim 15 , wherein: determining a selection value includes using an up/down counter to select said one of the delayed clock signals.
Claim 21
Dependent Claim
20 words
The method of claim 15 , wherein: said at least one characteristic includes a signal delay in the output circuit.
Claim 22
Dependent Claim
20 words
The method of claim 15 , wherein: said at least one characteristic includes an output load on the output circuit.
Claim 23
Dependent Claim
27 words
The method of claim 15 , wherein: providing multiple delayed clock signals includes providing clock signals with phase delays spanning a single cycle of the reference clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-07-11 | 2009-01-10 | 2009-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-07-11 | 2013-01-10 | 2013-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-07-11 | 2017-01-10 | 2017-07-12 | $7700.00 | Window Closed / Lapsed |