Patent US6914464B2 successfully refreshed from Google Patents.
US6914464B2
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US
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Phase locked loop circuit using fractional frequency divider
Assignee: Ando Electric Co Ltd
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Filing: 2003-07-16
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Granted: 2005-07-05
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Expires: 2023-07-16
Abstract
Abstract Phase-locked loop (PLL) circuits include first and second PLL stages and use fractional frequency division. In one implementation, the first stage includes a voltage-controlled oscillator (VCO) whose output is provided to both first and second fractional frequency dividers. The output of the first frequency divider is provided to a first phase comparator whose output passes through a filter so as to provide the deviation signal that controls the output frequency of the first VCO. The output of the second fractional frequency divider is received by the second PLL stage as a reference signal.
Inventors
- 👤 Minoru Maeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:39
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/1806; H03L7/197; H03L7/1974; H03L7/22; H03L7/23
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
115 words
A phase locked loop (PLL) circuit using a fractional frequency divider, comprising: a first PLL stage for controlling an output frequency of a first voltage-controlled oscillator with a deviation, which is obtained by dividing the frequency of the output of said first voltage-controlled oscillator by a first fractional frequency divider and by comparing the frequency-divided output with a first reference frequency in a first phase comparator whose output passes through a filter; and a second fractional frequency divider for dividing the frequency of the output from the first voltage-controlled oscillator of said first PLL stage; a second PLL stage for receiving an output of said second fractional frequency divider as a second reference frequency signal.
Claim 2
Dependent Claim
115 words
A phase locked loop (PLL) circuit using a fractional frequency divider, comprising: a first PLL stage for controlling an output frequency of a first voltage-controlled oscillator with a deviation, which is obtained by dividing the frequency of the output of said first voltage-controlled oscillator by a first fractional frequency divider and by comparing the frequency-divided output with a first reference frequency in a first phase comparator whose output passes through a filter; and a second fractional frequency divider for dividing the frequency of the output from the first voltage-controlled oscillator of said first PLL stage; a second PLL stage for receiving an output of said second fractional frequency divider as a second reference frequency signal.
Claim 3
Dependent Claim
62 words
A phase locked loop circuit using a fractional frequency divider, according to claim 1 , wherein said second PLL stage is constructed to control the output frequency of said second voltage-controlled oscillator by a frequency divider and by comparing the frequency-divided output from said frequency divider with the second reference frequency in a second phase comparator whose output passes through a filter.
Claim 4
Dependent Claim
177 words
A phase locked loop (PLL) circuit using a fractional frequency divider, comprising: a first PLL stage for controlling an output frequency of a first voltage-controlled oscillator in accordance with a deviation, which is obtained by comparing in a first phase comparator an output of said first voltage-controlled oscillator with a first reference frequency, wherein the output of the first voltage-controlled oscillator passes through a direct digital synthesizer (DDS) for multiplication by G/2 h ; and a second PLL stage for controlling an output frequency of a second voltage-controlled oscillator in accordance with a deviation, which is obtained by comparing in a second phase comparator the output of said second voltage-controlled oscillator with a signal that is frequency-divided from the output of the second voltage-controlled oscillator by a fractional frequency divider, with the output of said first PLL stage used as a second reference frequency signal, wherein frequency division by the fractional frequency divider is expressed by 1/(m+A/2 b ), wherein the value of 2 (h−b) /G is equal to a factorial of a positive integer of 10.
Claim 5
Dependent Claim
177 words
A phase locked loop (PLL) circuit using a fractional frequency divider, comprising: a first PLL stage for controlling an output frequency of a first voltage-controlled oscillator in accordance with a deviation, which is obtained by comparing in a first phase comparator an output of said first voltage-controlled oscillator with a first reference frequency, wherein the output of the first voltage-controlled oscillator passes through a direct digital synthesizer (DDS) for multiplication by G/2 h ; and a second PLL stage for controlling an output frequency of a second voltage-controlled oscillator in accordance with a deviation, which is obtained by comparing in a second phase comparator the output of said second voltage-controlled oscillator with a signal that is frequency-divided from the output of the second voltage-controlled oscillator by a fractional frequency divider, with the output of said first PLL stage used as a second reference frequency signal, wherein frequency division by the fractional frequency divider is expressed by 1/(m+A/2 b ), wherein the value of 2 (h−b) /G is equal to a factorial of a positive integer of 10.
Claim 6
Dependent Claim
160 words
A phase locked loop (PLL) circuit using a fractional frequency divider, comprising: a first PLL stage for controlling an output frequency of a first voltage-controlled oscillator with a deviation, which is obtained by frequency-dividing the output of said first voltage-controlled oscillator by a first fractional frequency and by comparing in a first phase comparator the frequency-divided output with a first reference frequency; and a second PLL stage for controlling an output frequency of a second voltage-controlled oscillator in accordance with a deviation, which is obtained by comparing an output of said second voltage-controlled oscillator passed through a direct digital synthesizer (DDS) for multiplying the output of said second stage voltage-controlled oscillator by G/2 h , with the output of said first PLL stage as a second reference frequency; wherein frequency division by the fractional frequency divider is expressed by 1/(m+A/2 b ), wherein the value of 2 (h−b) /G is equal to a factorial of a positive integer of 10.
Claim 7
Dependent Claim
160 words
A phase locked loop (PLL) circuit using a fractional frequency divider, comprising: a first PLL stage for controlling an output frequency of a first voltage-controlled oscillator with a deviation, which is obtained by frequency-dividing the output of said first voltage-controlled oscillator by a first fractional frequency and by comparing in a first phase comparator the frequency-divided output with a first reference frequency; and a second PLL stage for controlling an output frequency of a second voltage-controlled oscillator in accordance with a deviation, which is obtained by comparing an output of said second voltage-controlled oscillator passed through a direct digital synthesizer (DDS) for multiplying the output of said second stage voltage-controlled oscillator by G/2 h , with the output of said first PLL stage as a second reference frequency; wherein frequency division by the fractional frequency divider is expressed by 1/(m+A/2 b ), wherein the value of 2 (h−b) /G is equal to a factorial of a positive integer of 10.
Claim 8
Dependent Claim
41 words
A phase locked loop circuit using a fractional frequency divider, according to any of claims 1 , 3 and 4 , further comprising: a band-pass filter inserted into a front stage of the first phase comparator of said first PLL stage.
Claim 9
Dependent Claim
38 words
A phase-locked loop (PLL) circuit using a frequency divider, according to claim 1 wherein said second fractional frequency divider has a frequency division ratio of 1/(N+C/D) to output said reference frequency signal having a frequency of (N*D+C) Hz.
Claim 10
Dependent Claim
23 words
A phase-locked loop (PLL) circuit using a frequency divider according to claim 6 wherein the value of D is a factorial of 2.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2008-07-04 | 2009-01-03 | 2009-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-07-04 | 2013-01-03 | 2013-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-07-04 | 2017-01-03 | 2017-07-05 | $7700.00 | Window Closed / Lapsed |