Digitally-controlled oscillator with switched-capacitor frequency selection

Claim 2

The digitally-controlled oscillator, comprising: a plurality of switchable binary weighted capacitors for presenting a capacitance to a common node responsive to the state of a digital control word, each of said capacitors having a first plate coupled to receive a signal corresponding to a respective bit of the digital control word, and a second plate directly coupled to said common node; a Schmitt trigger having an input coupled to the common node, and an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage.

Claim 3

The digitally-controlled oscillator of claim 1 , wherein the inverting feedback logic comprises: a fixed delay stage, having an input coupled to the output of the Schmitt trigger; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node.

Claim 4

The digitally-controlled oscillator of claim 2 , further comprising: first and second reset transistors, each having a conduction path and a control terminal, the conduction paths of the first reset transistor connected between a power supply voltage and the common node, and the conduction path of the second reset transistor connected between the common node and a reference voltage; reset logic, having an input coupled to the output of the Schmitt trigger, and having outputs coupled to the control terminals of the first and second reset transistors, for turning on the first reset transistor responsive to a transition at the output of the Schmitt trigger indicating that the voltage at the common node has reached a first threshold of a logic level corresponding to the power supply voltage, and for turning on the second reset transistor responsive to a transition at the output of the Schmitt trigger indicating that the voltage at the common node has reached a second threshold of a logic level corresponding to the reference voltage.

Claim 5

The digitally-controlled oscillator of claim 3 , wherein the reset logic also has an input coupled to the output of the fixed delay stage, and turns off the first and second reset transistors responsive to a transition at the output of the fixed delay stage.

Claim 6

A digital phase-locked loop circuit, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phased relationship; a digitally-controlled oscillator, comprising: a plurality of switchable capacitors for presenting a capacitance to a common node responsive to the state of a digital control word, each of said capacitors having a first plate coupled to receive a signal corresponding to a respective bit of the digital control word, and a second plate directly coupled to said common node; a Schmitt trigger having an input coupled to the common node and having and output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage; and feedback circuitry, having an input coupled to an output of the digitally-controlled oscillator, and having an output for presenting the feedback clock signal to the phase frequency detector.

Claim 7

A digital phase-locked loop circuit, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phased relationship; a digitally-controlled oscillator, comprising: a plurality of switchable capacitors for presenting a capacitance to a common node responsive to the state of a digital control word, each of said capacitors having a first plate coupled to receive a signal corresponding to a respective bit of the digital control word, and a second plate directly coupled to said common node; a Schmitt trigger having an input coupled to the common node and having and output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage; and feedback circuitry, having an input coupled to an output of the digitally-controlled oscillator, and having an output for presenting the feedback clock signal to the phase frequency detector.

Claim 8

The digital phase-locked loop circuit of claim 5 , wherein the inverting feedback logic comprises: a fixed delay stage, having an input coupled to the output of the Schmitt trigger; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node.

Claim 9

The digital phase-locked loop circuit of claim 6 , wherein the digitally-controlled oscillator further comprises: first and second reset transistors, each having a conduction path and a control terminal, the conduction paths of the first reset transistor connected between a power supply voltage and the common node, and the conduction path of the second reset transistor connected between the common node and a reference voltage; reset logic, having an input coupled to the output of the Schmitt trigger, and having outputs coupled to the control terminals of the first and second reset transistors, for turning on the first reset transistor responsive to a transition at the output of the Schmitt trigger indicating that the voltage at the common node has reached a first threshold of a logic level corresponding to the power supply voltage, and for turning on the second reset transistor responsive to a transition at the output of the Schmitt trigger indicating that the voltage at the common node has reached a second threshold of a logic level corresponding to the reference voltage.

Claim 10

The digital phase-locked loop circuit of claim 7 , wherein the reset logic also has an input coupled to the output of the fixed delay stage, and turns off the first and second reset transistors responsive to a transition at the output of the fixed delay stage.

Claim 11

An electronic system, comprising: at least one input/output device; and an integrated circuit, coupled to the at least one input/output device, and comprising: functional circuitry, for executing logical operations upon digital data signal in a synchronous fashion according to an internal clock signal; power distribution circuitry, coupled to a battery, for distributing power to the functional circuitry; and a digital phase-locked loop circuit for generating the internal clock signal, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input clock signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phase relationship; a digitally-controlled oscillator, comprising: a plurality of switchable binarily-weighted capacitors, each of the plurality of capacitors coupled to a common node, for presenting a capacitance to the common node responsive to the state of an associated bit of the digital control word; output circuitry, having an input coupled to the common node, and having an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage; and feedback circuitry, having an input coupled to an output of the digitally-controlled oscillator, and having an output for presenting the feedback clock signal to the phase-frequency detector.

Claim 12

An electronic system, comprising: at least one input/output device; and an integrated circuit, coupled to the at least one input/output device, and comprising: functional circuitry, for executing logical operations upon digital data signal in a synchronous fashion according to an internal clock signal; power distribution circuitry, coupled to a battery, for distributing power to the functional circuitry; and a digital phase-locked loop circuit for generating the internal clock signal, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input clock signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phase relationship; a digitally-controlled oscillator, comprising: a plurality of switchable binarily-weighted capacitors, each of the plurality of capacitors coupled to a common node, for presenting a capacitance to the common node responsive to the state of an associated bit of the digital control word; output circuitry, having an input coupled to the common node, and having an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage; and feedback circuitry, having an input coupled to an output of the digitally-controlled oscillator, and having an output for presenting the feedback clock signal to the phase-frequency detector.

Claim 13

The system of claim 9 , wherein each of the plurality of switched capacitors has a first plate coupled to receive a signal corresponding to the associated bit of the digital control word, and has a second plate connected in common with the second plate of others of the plurality of capacitors at the common node.

Claim 14

The system of claim 9 , wherein the capacitance values of the plurality of switched capacitors vary in a binary-weighted fashion; wherein each of the plurality of switched capacitors has a first plate coupled to receive a signal corresponding to the associated bit of the digital control word, and has a second plate connected in common with the second plate of others of the plurality of switched capacitors at the common node; and wherein the first plate of a smallest of the plurality of switched capacitors is coupled to receive a least significant bit of the digital control word, and the first plate of a largest of the plurality of switched capacitors is coupled to receive a most significant bit of the digital control word.

Claim 15

An electronic system, comprising: at least one input/output device; and an integrated circuit, coupled to the at least one input/output device, and comprising: functional circuitry, for executing logical operations upon digital data signal in a synchronous fashion according to an internal clock signal; power distribution circuitry, coupled to a battery, for distributing power to the functional circuitry; and a digital phase-locked loop circuit for generating the internal clock signal, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input clock signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phase relationship; a digitally-controlled oscillator, comprising: a plurality of switchable binarily-weighted capacitors, each of the plurality of capacitors coupled to a common node, for presenting a capacitance to the common node responsive to the state of an associated bit of the digital control word; a Schmitt trigger having an input coupled to a common plate of the plurality of capacitors; inverting feedback logic comprising: a fixed delay stage, having an input coupled to the output of the Schmitt trigger; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node; wherein the digitally-controlled oscillator further comprises: first and second reset transistors, each having a conduction path and a control terminal, the conduction paths of the first reset transistor connected between a power supply voltage and the common node, and the conduction path of the second reset transistor connected between the common node and a reference voltage; reset logic, having an input coupled to the output of the Schmitt trigger, and having outputs coupled to the control terminals of the first and second reset transistors, for turning on the first reset transistor responsive to a transition at the output of the Schmitt trigger indicating that the voltage at the common node has reached a first threshold of a logic level corresponding to the power supply voltage, and for turning on the second reset transistor responsive to a transition at the output of the Schmitt trigger indicating that the voltage at the common node has reached a second threshold of a logic level corresponding to the reference voltage; and wherein the reset logic also has an input coupled to the output of the fixed delay stage, and turns off the first and second reset transistors responsive to a transition at the output of the fixed delay stage; and the inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage; and feedback circuitry, having an input coupled to an output of the digitally-controlled oscillator, and having an output for presenting the feedback clock signal to the phase-frequency detector.

Claim 16

An electronic system, comprising: at least one input/output device; and an integrated circuit, coupled to the at least one input/output device, and comprising: functional circuitry, for executing logical operations upon digital data signal in a synchronous fashion according to an internal clock signal; power distribution circuitry, coupled to a battery, for distributing power to the functional circuitry; and a digital phase-locked loop circuit for generating the internal clock signal, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input clock signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phase relationship; a digitally-controlled oscillator, comprising: a plurality of switchable binarily-weighted capacitors, each of the plurality of capacitors coupled to a common node, for presenting a capacitance to the common node responsive to the state of an associated bit of the digital control word; a Schmitt trigger having an input coupled to a common plate of the plurality of capacitors; inverting feedback logic comprising: a fixed delay stage, having an input coupled to the output of the Schmitt trigger; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node; wherein the digitally-controlled oscillator further comprises: first and second reset transistors, each having a conduction path and a control terminal, the conduction paths of the first reset transistor connected between a power supply voltage and the common node, and the conduction path of the second reset transistor connected between the common node and a reference voltage; reset logic, having an input coupled to the output of the Schmitt trigger, and having outputs coupled to the control terminals of the first and second reset transistors, for turning on the first reset transistor responsive to a transition at the output of the Schmitt trigger indicating that the voltage at the common node has reached a first threshold of a logic level corresponding to the power supply voltage, and for turning on the second reset transistor responsive to a transition at the output of the Schmitt trigger indicating that the voltage at the common node has reached a second threshold of a logic level corresponding to the reference voltage; and wherein the reset logic also has an input coupled to the output of the fixed delay stage, and turns off the first and second reset transistors responsive to a transition at the output of the fixed delay stage; and the inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage; and feedback circuitry, having an input coupled to an output of the digitally-controlled oscillator, and having an output for presenting the feedback clock signal to the phase-frequency detector.

Claim 17

The electronic system of claim 9 , wherein said binarily weighted capacitors are each controlled by one bit of a digital control word.

Claim 18

A digitally-controlled oscillator, comprising: a plurality of switchable binarily weighted capacitors for presenting a capacitance to a common node responsive to the state of a digital control word, each of said capacitors having a first plate coupled to receive a signal corresponding to a respective bit of the digital control word, and a second plate directly coupled to said common node; output circuitry, having an input coupled to the common node, and having an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage, said inverting feedback logic comprising: a fixed delay stage, having an input coupled to the output of the output circuitry; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node.

Claim 19

A digitally-controlled oscillator, comprising: a plurality of switchable binarily weighted capacitors for presenting a capacitance to a common node responsive to the state of a digital control word, each of said capacitors having a first plate coupled to receive a signal corresponding to a respective bit of the digital control word, and a second plate directly coupled to said common node; output circuitry, having an input coupled to the common node, and having an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage, said inverting feedback logic comprising: a fixed delay stage, having an input coupled to the output of the output circuitry; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node.

Claim 20

The digitally-controlled oscillator of claim 14 , wherein said binarily weighted capacitors are each controlled by one bit of a digital control word such that load capacitance on said delay stage is proportional to the value of the control word.

Claim 21

A digital phase-locked loop circuit, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input clock signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phase relationship; a digitally-controlled oscillator, comprising: a plurality of switchable capacitors for presenting a capacitance to a common node responsive to the state of a digital control word, each of said capacitors having a first plate coupled to receive a signal corresponding to a respective bit of the digital control word, and a second plate directly coupled to said common node; output circuitry, having an input coupled to the common node, and having an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage, said inverting feedback logic comprising: a fixed delay stage, having an input coupled to the output of the output circuitry; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node; and feedback circuitry, having an input coupled to an output of the digitally-controlled oscillator, and having an output for presenting the feedback clock signal to the phase-frequency detector.

Claim 22

A digital phase-locked loop circuit, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input clock signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phase relationship; a digitally-controlled oscillator, comprising: a plurality of switchable capacitors for presenting a capacitance to a common node responsive to the state of a digital control word, each of said capacitors having a first plate coupled to receive a signal corresponding to a respective bit of the digital control word, and a second plate directly coupled to said common node; output circuitry, having an input coupled to the common node, and having an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage, said inverting feedback logic comprising: a fixed delay stage, having an input coupled to the output of the output circuitry; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node; and feedback circuitry, having an input coupled to an output of the digitally-controlled oscillator, and having an output for presenting the feedback clock signal to the phase-frequency detector.

Claim 23

The digital phase-locked loop circuit of claim 16 , wherein the plurality of switchable capacitors are each controlled by one bit of a digital control word such that load capacitance on said delay stage is proportional to the value of the control word.

Claim 24

An electronic system, comprising: at least one input/output device; and an integrated circuit, coupled to the at least one input/output device, and comprising: functional circuitry, for executing logical operations upon digital data signal in a synchronous fashion according to an internal clock signal; power distribution circuitry, coupled to a battery, for distributing power to the functional circuitry; and a digital phase-locked loop circuit for generating the internal clock signal, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input clock signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phase relationship; a digitally-controlled oscillator, comprising: a plurality of switchable binarily-weighted capacitors, each of the plurality of capacitors coupled to a common node, for presenting a capacitance to the common node responsive to the state of an associated bit of the digital control word; output circuitry, having an input coupled to the common node, and having an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage, said inverting feedback logic comprising: a fixed delay stage, having an input coupled to the output of the output circuitry; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node; and feedback circuitry, having an input coupled to an output of the driver circuitry, and having an output for presenting the feedback clock signal to the phase-frequency detector.

Claim 25

An electronic system, comprising: at least one input/output device; and an integrated circuit, coupled to the at least one input/output device, and comprising: functional circuitry, for executing logical operations upon digital data signal in a synchronous fashion according to an internal clock signal; power distribution circuitry, coupled to a battery, for distributing power to the functional circuitry; and a digital phase-locked loop circuit for generating the internal clock signal, comprising: a phase-frequency detector, having inputs receiving an input clock signal and a feedback clock signal, for detecting a phase relationship between the input clock signal and the feedback clock signal; a loop filter, coupled to the phase-frequency detector, for adjusting a digital control word responsive to the detected phase relationship; a digitally-controlled oscillator, comprising: a plurality of switchable binarily-weighted capacitors, each of the plurality of capacitors coupled to a common node, for presenting a capacitance to the common node responsive to the state of an associated bit of the digital control word; output circuitry, having an input coupled to the common node, and having an output for driving an output clock signal; and inverting feedback logic, having an input coupled to the common node and having an output for driving the common node to a complementary voltage, said inverting feedback logic comprising: a fixed delay stage, having an input coupled to the output of the output circuitry; and a driver, having an input coupled to an output of the fixed delay stage, and having an output coupled to the common node; and feedback circuitry, having an input coupled to an output of the driver circuitry, and having an output for presenting the feedback clock signal to the phase-frequency detector.

Claim 26

The electronic system of claim 18 , wherein said binarily weighted capacitors are each controlled by one bit of a digital control word such that load capacitance on said delay stage is proportional to the value of the control word.