Vertical transistors and output prediction logic circuits containing same

Claim 2

A vertical MOS transistor comprising: a semiconductor substrate; a relaxed silicon germanium region formed over said substrate, said relaxed silicon germanium region having a graded germanium content; source and drain regions disposed on respective top and bottom sides of said relaxed silicon germanium region and in contact with said relaxed silicon germanium region; and a strained silicon layer in contact with said relaxed silicon germanium region.

Claim 3

The vertical MOS transistor of claim 1 further comprising a silicon oxide layer in contact with said strained silicon layer.

Claim 4

The vertical MOS transistor of claim 2 further comprising a vertical transistor gate in contact with said silicon oxide layer.

Claim 5

The vertical MOS transistor of claim 3 , wherein said vertical transistor gate is a polysilicon gate.

Claim 6

The vertical MOS transistor of claim 1 , wherein said relaxed silicon germanium layer has a thickness of about 2,000 Angstroms to about 40,000 Angstroms between said source and drain regions.

Claim 7

The vertical MOS transistor of claim 1 , wherein said relaxed silicon germanium layer is an epitaxially grown layer.

Claim 8

The vertical MOS transistor of claim 1 , wherein said relaxed silicon germanium layer has a graded germanium content of about 0% to about 20%.

Claim 9

The vertical MOS transistor of claim 1 , wherein said strained silicon layer has a thickness of about 200 Angstroms to about 2,000 Angstroms.

Claim 10

The vertical MOS transistor of claim 1 , wherein said source and drain layer is an n+ silicon layer and said vertical MOS transistor is an NMOS transistor.

Claim 11

The vertical MOS transistor of claim 1 , wherein said strained silicon layer is under a biaxial tensile strain.

Claim 12

The vertical MOS transistor of claim 1 , wherein said semiconductor substrate is a silicon substrate.

Claim 13

A vertical NMOS transistor comprising: a silicon substrate; a relaxed silicon germanium region formed over said silicon substrate, said relaxed silicon germanium region having a graded germanium content from about 0% to about 20%, said relaxed silicon germanium region having a top surface and a bottom surface; source and drain regions disposed on opposite sides of said relaxed silicon germanium region so that one of said source and drain regions is provided over and in contact with said top surface of said relaxed silicon germanium region, and the other of said source and drain regions is provided below and in contact with said bottom surface of said relaxed silicon germanium region; and a strained silicon layer in contact with said relaxed silicon germanium region with graded germanium content.

Claim 14

A vertical NMOS transistor comprising: a silicon substrate; a relaxed silicon germanium region formed over said silicon substrate, said relaxed silicon germanium region having a graded germanium content from about 0% to about 20%, said relaxed silicon germanium region having a top surface and a bottom surface; source and drain regions disposed on opposite sides of said relaxed silicon germanium region so that one of said source and drain regions is provided over and in contact with said top surface of said relaxed silicon germanium region, and the other of said source and drain regions is provided below and in contact with said bottom surface of said relaxed silicon germanium region; and a strained silicon layer in contact with said relaxed silicon germanium region with graded germanium content.

Claim 15

The vertical NMOS transistor of claim 12 further comprising a silicon oxide layer in contact with said strained silicon layer.

Claim 16

The vertical NMOS transistor of claim 13 further comprising a vertical polysilicon gate in contact with said silicon oxide layer.

Claim 17

The vertical NMOS transistor of claim 12 , wherein said relaxed silicon germanium layer is an epitaxially grown layer by ultra high vacuum chemical vapor deposition.

Claim 18

The vertical NMOS transistor of claim 12 , wherein said strained silicon layer is under a biaxial tensile strain.

Claim 19

A pseudo-NMOS output prediction logic circuit comprising: a plurality of logic inputs, a clock input and an output, wherein each of said plurality of logic inputs is coupled to a plurality of gates of vertical NMOS transistors comprising a relaxed silicon germanium region with a graded germanium content of about 15% to about 20% and a strained silicon channel in contact with said relaxed silicon germanium region, and wherein the dock output is coupled to a gate of a vertical PMOS transistor for precharging the output high.

Claim 20

A pseudo-NMOS output prediction logic circuit comprising: a plurality of logic inputs, a clock input and an output, wherein each of said plurality of logic inputs is coupled to a plurality of gates of vertical NMOS transistors comprising a relaxed silicon germanium region with a graded germanium content of about 15% to about 20% and a strained silicon channel in contact with said relaxed silicon germanium region, and wherein the dock output is coupled to a gate of a vertical PMOS transistor for precharging the output high.

Claim 21

A dynamic output prediction logic circuit comprising: a plurality of logic inputs, a clock input and an output, wherein each of said plurality of logic inputs is coupled to a plurality of gates of vertical NMOS transistors comprising a relaxed silicon germanium region with a graded germanium content of about 15% to about 20% and a strained silicon channel in contact with said relaxed silicon germanium region, and wherein the clock output is coupled to a gate of a vertical PMOS transistor for precharging the output high.

Claim 22

A dynamic output prediction logic circuit comprising: a plurality of logic inputs, a clock input and an output, wherein each of said plurality of logic inputs is coupled to a plurality of gates of vertical NMOS transistors comprising a relaxed silicon germanium region with a graded germanium content of about 15% to about 20% and a strained silicon channel in contact with said relaxed silicon germanium region, and wherein the clock output is coupled to a gate of a vertical PMOS transistor for precharging the output high.

Claim 23

A processor-based system comprising: a processor; and an integrated circuit coupled to said processor, at least one of said integrated circuit and said processor comprising a vertical NMOS transistor including a relaxed silicon germanium body region with a graded germanium content of about 15% to about 20%; a strained silicon layer in contact with said relaxed silicon germanium body region; and source and drain regions formed adjacent said relaxed silicon germanium body region with said graded germanium content.

Claim 24

A processor-based system comprising: a processor; and an integrated circuit coupled to said processor, at least one of said integrated circuit and said processor comprising a vertical NMOS transistor including a relaxed silicon germanium body region with a graded germanium content of about 15% to about 20%; a strained silicon layer in contact with said relaxed silicon germanium body region; and source and drain regions formed adjacent said relaxed silicon germanium body region with said graded germanium content.