Patent US6894914B2 successfully refreshed from Google Patents.
US6894914B2
Expired / Lapsed
US
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Nonvolatile memory device with parallel and serial functioning mode and selectable communication protocol
Assignee: STMicroelectronics SRL
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Filing: 2002-10-11
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Granted: 2005-05-17
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Expires: 2022-10-11
Abstract
Abstract An architecture of a nonvolatile memory device, though not requiring dedicated pins and by introducing circuit modifications that require a negligible additional silicon area in the serial interface, allows a selection between at least two different serial communication protocols, thus multiplying the occasions of employment of the same device. The selection of one or of the another serial communication protocol is carried out by setting, during the testing on wafer (EWS) of the devices being fabricated, a certain UPROM cell of the array of UPROM cells that is normally present in a standard nonvolatile memory device for setting during the fabrication the characteristics of ATD, redundancy and other functions of the memory device. Alternatively, the customer can make the selection by placing an appropriate signal level on a specified pin of the memory device.
Inventors
- 👤 Maurizio Perroni
- 👤 Salvatore Polizzi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:03
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C7/00; G11C7/10; G11C7/1006; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/22; G11C2207/2254
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
151 words
A memory device comprising a nonvolatile standard memory, an array of programmable read only cells for setting during a testing on wafer phase functional parameters of the memory, a serial interface for implementing a certain serial communication protocol, a parallel interface, an input/output data bus to the lines of which are coupled said interfaces and whose lines correspond to as many I/O pins of the device, characterized in that it comprises logic circuits in said serial interface, each implementing when selectively enabled, a specific serial communication protocol; a selection circuit of one of said serial communication protocols, selectable either permanently settable during the testing on wafer by programming a dedicated cell of said array of read only cells or by an externally applied logic command through a I/O pin; the output buffer of said I/O pin being disabled by a disabling signal during the functioning in serial mode of the memory.
Claim 2
Dependent Claim
151 words
A memory device comprising a nonvolatile standard memory, an array of programmable read only cells for setting during a testing on wafer phase functional parameters of the memory, a serial interface for implementing a certain serial communication protocol, a parallel interface, an input/output data bus to the lines of which are coupled said interfaces and whose lines correspond to as many I/O pins of the device, characterized in that it comprises logic circuits in said serial interface, each implementing when selectively enabled, a specific serial communication protocol; a selection circuit of one of said serial communication protocols, selectable either permanently settable during the testing on wafer by programming a dedicated cell of said array of read only cells or by an externally applied logic command through a I/O pin; the output buffer of said I/O pin being disabled by a disabling signal during the functioning in serial mode of the memory.
Claim 3
Dependent Claim
34 words
The device according to claim 1 , characterized in that said I/O pin corresponds to a line of said input/output data bus that is not used when the memory is functioning in serial mode.
Claim 4
Dependent Claim
61 words
The memory device according to claim 1 , characterized in that said different serial communication protocols are of an LPC kind and said serial interface is composed by a common interface circuitry and by distinct logic circuits of implementation of respectively different LPC serial communication protocols, enabled in a mutual exclusive manner by an enabling signal generated by said selection circuit.
Claim 5
Dependent Claim
50 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; and a first interface coupled to the array and to the bus and operatable to receive a protocol-selection signal that causes the first interface to operate according to a corresponding one of at least two protocols.
Claim 6
Dependent Claim
50 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; and a first interface coupled to the array and to the bus and operatable to receive a protocol-selection signal that causes the first interface to operate according to a corresponding one of at least two protocols.
Claim 7
Dependent Claim
18 words
The memory of claim 4 , further comprising second interface coupled to the array and to the bus.
Claim 8
Dependent Claim
13 words
The memory of claim 4 wherein the first interface comprises a serial interface.
Claim 9
Dependent Claim
20 words
The memory of claim 4 wherein the first interface is coupled to some but not all of the bus lines.
Claim 10
Dependent Claim
79 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a first interface coupled to the array and to the bus and operable to interface all of the bus lines to the array; and a second interface coupled to the array and to the bus and operable to receive a protocol-selection value and to interface some but not all of the bus lines to the array according to a protocol selected by the protocol-selection value.
Claim 11
Dependent Claim
79 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a first interface coupled to the array and to the bus and operable to interface all of the bus lines to the array; and a second interface coupled to the array and to the bus and operable to receive a protocol-selection value and to interface some but not all of the bus lines to the array according to a protocol selected by the protocol-selection value.
Claim 12
Dependent Claim
12 words
The memory of claim 8 wherein the array comprises nonvolatile memory cells.
Claim 13
Dependent Claim
16 words
The memory of claim 8 wherein the bus comprises a data bus having multiple data lines.
Claim 14
Dependent Claim
111 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a first interface coupled to the array and to the bus and operable to interface all of the bus lines to the array; a second interface coupled to the array and to the bus and operable to receive a protocol-selection value and to interface some but not all of the bus lines to the array according to a protocol selected by the protocol-selection value; and a configuration-selection cell coupled to the second interface and operable to be programmed with the protocol-selection value during testing of the memory and to provide the protocol-selection value to the second interface.
Claim 15
Dependent Claim
111 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a first interface coupled to the array and to the bus and operable to interface all of the bus lines to the array; a second interface coupled to the array and to the bus and operable to receive a protocol-selection value and to interface some but not all of the bus lines to the array according to a protocol selected by the protocol-selection value; and a configuration-selection cell coupled to the second interface and operable to be programmed with the protocol-selection value during testing of the memory and to provide the protocol-selection value to the second interface.
Claim 16
Dependent Claim
114 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a first interface coupled to the array and to the bus and operable to interface all of the bus lines to the array; a second interface coupled to the array and to the bus and operable to receive a protocol-selection value and to interface some but not all of the bus lines to the array according to a protocol selected by the protocol-selection value; and wherein the second interface is coupled to one of the bus lines that the second interface does not interface to the array and is operable to receive the protocol-selection value via the one bus line.
Claim 17
Dependent Claim
114 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a first interface coupled to the array and to the bus and operable to interface all of the bus lines to the array; a second interface coupled to the array and to the bus and operable to receive a protocol-selection value and to interface some but not all of the bus lines to the array according to a protocol selected by the protocol-selection value; and wherein the second interface is coupled to one of the bus lines that the second interface does not interface to the array and is operable to receive the protocol-selection value via the one bus line.
Claim 18
Dependent Claim
144 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a first interface coupled to the array and to the bus and operable to interface all of the bus lines to the array; a second interface coupled to the array and to the bus and operable to receive a protocol-selection value and to interface some but not all of the bus lines to the array according to a protocol selected by the protocol-selection value; a configuration-selection cell coupled to the second interface and operable to be programmed with the protocol-selection value during testing of the memory; wherein one of the bus lines that the second interface does not interface to the array is operable to receive the protocol-selection value; and a multiplexer operable to selectively couple one of the configuration-selection cell and the one bus line to the second interface.
Claim 19
Dependent Claim
144 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a first interface coupled to the array and to the bus and operable to interface all of the bus lines to the array; a second interface coupled to the array and to the bus and operable to receive a protocol-selection value and to interface some but not all of the bus lines to the array according to a protocol selected by the protocol-selection value; a configuration-selection cell coupled to the second interface and operable to be programmed with the protocol-selection value during testing of the memory; wherein one of the bus lines that the second interface does not interface to the array is operable to receive the protocol-selection value; and a multiplexer operable to selectively couple one of the configuration-selection cell and the one bus line to the second interface.
Claim 20
Dependent Claim
57 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; and a serial interface coupled to the array and to the bus and configurable to operate according to a selected one of at least two protocols in response to a protocol-selection signal.
Claim 21
Dependent Claim
57 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; and a serial interface coupled to the array and to the bus and configurable to operate according to a selected one of at least two protocols in response to a protocol-selection signal.
Claim 22
Dependent Claim
85 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; and a configuration-selection cell coupled to the serial interface and operable to be programmed with a protocol-selection value during testing of the memory, the protocol-selection value operable to configure the serial interface to operate according to a corresponding protocol.
Claim 23
Dependent Claim
85 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; and a configuration-selection cell coupled to the serial interface and operable to be programmed with a protocol-selection value during testing of the memory, the protocol-selection value operable to configure the serial interface to operate according to a corresponding protocol.
Claim 24
Dependent Claim
93 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; the second interface is coupled to one of the bus lines that the second interface does not interface to the array; and wherein the one bus line is operable to receive a protocol-selection value operable to configure the serial interface to operate according to a corresponding protocol.
Claim 25
Dependent Claim
93 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; the second interface is coupled to one of the bus lines that the second interface does not interface to the array; and wherein the one bus line is operable to receive a protocol-selection value operable to configure the serial interface to operate according to a corresponding protocol.
Claim 26
Dependent Claim
129 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; a configuration-selection cell coupled to the serial interface and operable to be programmed with a first protocol-selection value during testing of the memory; wherein one of the bus lines that the second interface does not interface to the array is operable to receive a second protocol-selection value; and a selection circuit coupled to the configuration-selection cell and to the one bus line and operable to configure the serial interface to operate according to a selected one of the first and second protocol-selection values.
Claim 27
Dependent Claim
129 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; a configuration-selection cell coupled to the serial interface and operable to be programmed with a first protocol-selection value during testing of the memory; wherein one of the bus lines that the second interface does not interface to the array is operable to receive a second protocol-selection value; and a selection circuit coupled to the configuration-selection cell and to the one bus line and operable to configure the serial interface to operate according to a selected one of the first and second protocol-selection values.
Claim 28
Dependent Claim
75 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; wherein the serial interface further comprises, a respective protocol circuit corresponding to each of the at least two protocols, and a common interface circuit coupled to the protocol circuits.
Claim 29
Dependent Claim
75 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; wherein the serial interface further comprises, a respective protocol circuit corresponding to each of the at least two protocols, and a common interface circuit coupled to the protocol circuits.
Claim 30
Dependent Claim
60 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; and wherein one of the at least two protocols comprises a low-pin-count (LPC) protocol.
Claim 31
Dependent Claim
60 words
A memory, comprising: an array of memory cells; a bus having multiple bus lines; a parallel interface coupled to the array and to the bus; a serial interface coupled to the array and to the bus and configurable to operate according to at least two protocols; and wherein one of the at least two protocols comprises a low-pin-count (LPC) protocol.
Claim 32
Independent Claim
35 words
A method, comprising: selecting a protocol with a protocol-selection signal; configuring an interface according to the selected protocol, the interface configurable in multiple protocols; and transferring information via the interface according to the selected protocol.
Claim 33
Independent Claim
35 words
A method, comprising: selecting a protocol with a protocol-selection signal; configuring an interface according to the selected protocol, the interface configurable in multiple protocols; and transferring information via the interface according to the selected protocol.
Claim 34
Dependent Claim
30 words
The method of claim 20 wherein: configuring the interface comprises enabling a protocol circuit that corresponds to the selected protocol; and transferring information comprises transferring information using the protocol circuit.
Claim 35
Independent Claim
54 words
A method, comprising: configuring an interface according to a protocol, the interface configurable in multiple protocols; transferring information via the interface according to the protocol; wherein configuring the interface comprises enabling a protocol circuit that corresponds to the protocol; and wherein transferring information comprises transferring information using the protocol circuit and a non-protocol-specific circuit.
Claim 36
Independent Claim
54 words
A method, comprising: configuring an interface according to a protocol, the interface configurable in multiple protocols; transferring information via the interface according to the protocol; wherein configuring the interface comprises enabling a protocol circuit that corresponds to the protocol; and wherein transferring information comprises transferring information using the protocol circuit and a non-protocol-specific circuit.
Claim 37
Independent Claim
35 words
A method, comprising: configuring an interface according to a protocol, the interface configurable in multiple protocols; transferring information via the interface according to the protocol; and wherein configuring the interface comprises programming a protocol-selection element.
Claim 38
Independent Claim
35 words
A method, comprising: configuring an interface according to a protocol, the interface configurable in multiple protocols; transferring information via the interface according to the protocol; and wherein configuring the interface comprises programming a protocol-selection element.
Claim 39
Independent Claim
48 words
A method, comprising: configuring an interface according to a protocol, the interface configurable in multiple protocols; transferring information via the interface according to the protocol; and wherein configuring the interface comprises programming a protocol-selection element during testing of an integrated circuit that incorporates the interface and the element.
Claim 40
Independent Claim
48 words
A method, comprising: configuring an interface according to a protocol, the interface configurable in multiple protocols; transferring information via the interface according to the protocol; and wherein configuring the interface comprises programming a protocol-selection element during testing of an integrated circuit that incorporates the interface and the element.
Claim 41
Dependent Claim
23 words
The method of claim 20 wherein selecting the protocol comprises selecting the protocol with a protocol-selection signal that is coupled to the interface.
References Cited (Backward Citations)
US6311263B1
Cited
US5896534A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-05-16 | 2008-11-15 | 2009-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-05-16 | 2012-11-15 | 2013-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-05-16 | 2016-11-15 | 2017-05-17 | $7700.00 | Window Closed / Lapsed |