Patent US6868376B2 successfully refreshed from Google Patents.
US6868376B2
Expired / Lapsed
US
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Debug bi-phase export and data recovery
Assignee: Texas Instruments Inc
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Filing: 2000-12-19
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Granted: 2005-03-15
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Expires: 2020-12-19
Abstract
Abstract An debug and emulation system includes a target device embodied in a single integrated circuit. The target device includes a function clock circuit and an operation circuit operating in synchronism with the function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. The trace data is sensed in synchronism with the oscillator clock. The emulator is coupled to the target device to control the clock selection. Accordingly, the trace export can operate at a frequency independent of the operation circuit.
Inventors
- 👤 Gary L. Swoboda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:47
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/3648; G06F11/3656
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
223 words
A debug and emulation system comprising: a target device embodied in a single integrated circuit including a function clock circuit generating a function clock; an operation circuit connected to said function clock circuit operating in synchronism with said function clock; a trace trigger circuit connected to said function clock circuit and said operation circuit, said trace trigger circuit triggering trace of operation of said operation circuit upon detection of a predetermined condition within said operation circuit; a reference clock input for receiving a reference clock signal; a clock circuit connected to said function clock circuit for receiving said function clock signal and to said reference clock input for receiving said reference clock signal, said clock circuit generating an oscillator clock signal synchronous with one of said function clock circuit and said reference clock signal; a trace first-in-first-out buffer having an input connected to said function clock circuit and said operation circuit for storing trace data in synchronism with said function clock signal and an output connected to said clock circuit for outputting trace data in synchronism with said oscillator clock signal; and a trace output port connected to said output of said trace first-in-first-out buffer outputting trace data from said target device; and an emulator connected to said trace output port for sensing said trace data in synchronism with said oscillator clock signal.
Claim 2
Dependent Claim
223 words
A debug and emulation system comprising: a target device embodied in a single integrated circuit including a function clock circuit generating a function clock; an operation circuit connected to said function clock circuit operating in synchronism with said function clock; a trace trigger circuit connected to said function clock circuit and said operation circuit, said trace trigger circuit triggering trace of operation of said operation circuit upon detection of a predetermined condition within said operation circuit; a reference clock input for receiving a reference clock signal; a clock circuit connected to said function clock circuit for receiving said function clock signal and to said reference clock input for receiving said reference clock signal, said clock circuit generating an oscillator clock signal synchronous with one of said function clock circuit and said reference clock signal; a trace first-in-first-out buffer having an input connected to said function clock circuit and said operation circuit for storing trace data in synchronism with said function clock signal and an output connected to said clock circuit for outputting trace data in synchronism with said oscillator clock signal; and a trace output port connected to said output of said trace first-in-first-out buffer outputting trace data from said target device; and an emulator connected to said trace output port for sensing said trace data in synchronism with said oscillator clock signal.
Claim 3
Dependent Claim
63 words
The debug and emulation system of claim 1 , wherein: said emulator includes a reference clock generator connected to said reference clock input for generating said reference clock signal; and a clock control circuit connected to said clock circuit of said target device for controlling whether said oscillator clock signal is synchronous with said function clock circuit or with said reference clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-03-14 | 2008-09-13 | 2009-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-03-14 | 2012-09-13 | 2013-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-03-14 | 2016-09-13 | 2017-03-15 | $7700.00 | Window Closed / Lapsed |