US6844766B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
VCDL with linear delay characteristics and differential duty-cycle correction
Assignee: Infineon Technologies AG
•
Filing: 2003-03-28
•
Granted: 2005-01-18
•
Expires: 2023-03-28
Abstract
Abstract A voltage-controlled delay line (VCDL) comprises a series of delay cells outputting a clock output signal having a delay relative to a clock input signal input to the series of delay cells. A duty-cycle correction section corrects the duty cycle of the clock output signal by providing opposite current outputs which are fed back to the series of delay cells to substantially simultaneously charge and discharge current of the series of delay cells in opposite directions. A control current input to the series of delay cells controls the amount of the delay. A voltage-to-current converter converts a control voltage into the control current so that the delay changes substantially linearly as the control voltage changes. The method for using the VCDL to produce linear delay is also included. The VCDL can be used in a delay-locked loop (DLL).
Inventors
- 👤 Jing Sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:27
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H03H11/265
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
109 words
A voltage-controlled delay line comprising: a series of delay cells outputting a clock output signal having a delay relative to a clock input signal input to the series of delay cells; a duty-cycle correction section for correcting the duty cycle of the clock output signal; a control current input to the series of delay cells to control the amount of the delay; a voltage-to-current converter for converting a control voltage into the control current so that the delay changes substantially linearly as the control voltage changes; and wherein the duty-cycle correction section samples the clock output signal to feed duty-cycle correction signals back to the series of delay cells.
Claim 2
Dependent Claim
109 words
A voltage-controlled delay line comprising: a series of delay cells outputting a clock output signal having a delay relative to a clock input signal input to the series of delay cells; a duty-cycle correction section for correcting the duty cycle of the clock output signal; a control current input to the series of delay cells to control the amount of the delay; a voltage-to-current converter for converting a control voltage into the control current so that the delay changes substantially linearly as the control voltage changes; and wherein the duty-cycle correction section samples the clock output signal to feed duty-cycle correction signals back to the series of delay cells.
Claim 3
Dependent Claim
25 words
The voltage-controlled delay line of claim 1 wherein the series of delay cells have substantially linear delay characteristics over a range of the control current.
Claim 4
Dependent Claim
36 words
The voltage-controlled delay line of claim 2 wherein the voltage-to-current converter converts the control voltage into the control current over a range of the control current for which the delay cells have substantially linear delay characteristics.
Claim 5
Dependent Claim
29 words
The voltage-controlled delay line of claim 1 wherein the series of delay cells is comprised of differential inverter delay cells each having two clock inputs and two clock outputs.
Claim 6
Dependent Claim
37 words
The voltage-controlled delay line of claim 4 wherein the two clock outputs of a delay cell of the series of delay cells supplies the two clock inputs of another delay cell of the series of delay cells.
Claim 7
Dependent Claim
50 words
The voltage-controlled delay line of claim 4 , wherein the duty-cycle correction section includes first and second duty cycle correction circuits with each circuit sampling a different one of the two clock outputs and providing feedback to substantially simultaneously charge and discharge current of the delay cells in opposite directions.
Claim 8
Dependent Claim
35 words
The voltage-controlled delay line of claim 6 , further comprising first and second busses connecting the first and second duty cycle correction circuits to first and second current mirrors of the series of delay cells.
Claim 9
Dependent Claim
26 words
The voltage-controlled delay line of claim 1 further comprising a current adder for adding current to the control current to drive the series of delay cells.
Claim 10
Dependent Claim
19 words
The voltage-controlled delay line of claim 1 wherein the duty-cycle correction section includes a duty cycle correcting voltage-to-current converter.
Claim 11
Dependent Claim
59 words
The voltage-controlled delay line of claim 9 wherein the duty cycle correcting voltage-to-current converter has first and second current outputs, the first current output outputting a current which increases with increasing voltage sampled from one of the clock outputs and the second current output outputting a current which decreases with increasing voltage sampled from another of the clock outputs.
Claim 12
Dependent Claim
26 words
The voltage-controlled delay line of claim 1 wherein the duty-cycle correction section includes a charge pump, low pass filter and a duty cycle correcting voltage-to-current converter.
Claim 13
Dependent Claim
14 words
A delay locked loop utilizing voltage-controlled delay line of claim 1 to provide delay.
Claim 14
Independent Claim
200 words
A method for providing linear delay relative to a control voltage compromising the steps of: inputting an differential input clock signal into a series of delay cells; inputting a control voltage into a voltage-to-current converter; inputting a control current output from the voltage-to-current converter into the series of delay cells; outputting a differential output clock voltage from the series of delay cells having a delay relative to the input clock voltage; varying the control voltage to vary the delay by an amount substantially directly proportional to the amount the control voltage is varied and further comprising the steps of: sampling the differential output clock voltage using first and second duty cycle correction circuits; converting, in each of the first and second duty cycle correction circuits, the sampled voltages into a first duty cycle correcting current which increases with increasing sampled voltage and into a second duty cycle correcting current which decreases with increasing sampled voltage; feeding the first and second duty cycle correcting currents from the duty cycle correction circuits to current mirrors in the series of delay cells to substantially simultaneously charge and discharge current of the series of delay cells in opposite directions to correct the duty cycle.
Claim 15
Independent Claim
200 words
A method for providing linear delay relative to a control voltage compromising the steps of: inputting an differential input clock signal into a series of delay cells; inputting a control voltage into a voltage-to-current converter; inputting a control current output from the voltage-to-current converter into the series of delay cells; outputting a differential output clock voltage from the series of delay cells having a delay relative to the input clock voltage; varying the control voltage to vary the delay by an amount substantially directly proportional to the amount the control voltage is varied and further comprising the steps of: sampling the differential output clock voltage using first and second duty cycle correction circuits; converting, in each of the first and second duty cycle correction circuits, the sampled voltages into a first duty cycle correcting current which increases with increasing sampled voltage and into a second duty cycle correcting current which decreases with increasing sampled voltage; feeding the first and second duty cycle correcting currents from the duty cycle correction circuits to current mirrors in the series of delay cells to substantially simultaneously charge and discharge current of the series of delay cells in opposite directions to correct the duty cycle.
References Cited (Backward Citations)
US5012142A
Cited
US5231320A
Cited
US5757873A
Cited
US5559476A
Cited
US6081146A
Cited
US6703879B2
Cited
US6411145B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2008-01-18 | 2008-07-19 | 2009-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-01-18 | 2012-07-19 | 2013-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2016-01-18 | 2016-07-19 | 2017-01-18 | $7700.00 | Window Closed / Lapsed |