Patent US6844761B2 successfully refreshed from Google Patents.
US6844761B2
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DLL with false lock protector
Assignee: Qualcomm Inc
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Filing: 2003-05-12
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Granted: 2005-01-18
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Expires: 2023-05-12
Abstract
Abstract A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.
Inventors
- 👤 Sang Jin Byun
- 👤 Beomsup Kim
- 👤 Chan-Hong Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:45
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/081; H03L7/0812; H03L7/0816; H03L2207/00; H03L2207/14
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
130 words
A delay locked loop for false lock protection comprising: a reference clock sending a first signal; a delay line for delaying the first signal and sending a second signal to an output clock; a phase detector for detecting a phase in the first signal and the second signal; a comparator for comparing an order of a rising edge of the second signal with a rising edge of the first signal and generating output data; a determinator, using the output data from the comparator, for determining a range to be associated with the rising edge of the second signal, with regard to the reference clock; and a controller for controlling the delay line using the phase detector and the output data from the comparator and the range determined by the determinator.
Claim 2
Dependent Claim
130 words
A delay locked loop for false lock protection comprising: a reference clock sending a first signal; a delay line for delaying the first signal and sending a second signal to an output clock; a phase detector for detecting a phase in the first signal and the second signal; a comparator for comparing an order of a rising edge of the second signal with a rising edge of the first signal and generating output data; a determinator, using the output data from the comparator, for determining a range to be associated with the rising edge of the second signal, with regard to the reference clock; and a controller for controlling the delay line using the phase detector and the output data from the comparator and the range determined by the determinator.
Claim 3
Dependent Claim
16 words
The delay locked loop of claim 1 wherein the range is a fast false lock range.
Claim 4
Dependent Claim
14 words
The delay locked loop of claim 1 wherein the range is a lock range.
Claim 5
Dependent Claim
16 words
The delay locked loop of claim 1 wherein the range is a slow false lock range.
Claim 6
Dependent Claim
54 words
The delay locked loop of claim 1 wherein the controller further comprises: a capacitor for storing a charge, wherein the charge determines an amount of delay in the first signal; and a charge pump for charging or discharging the capacitor, wherein the charging or discharging is based on the output data and the range.
Claim 7
Dependent Claim
17 words
The delay locked loop of claim 1 wherein the comparator is further comprised of a delayed flip-flop.
Claim 8
Dependent Claim
50 words
The delay locked loop of claim 1 wherein the determinator generates a discharge control signal to discharge the capacitor if a 1 a 2 . . . a n =1, wherein a 1 , a 2 , . . . a n are binary digital output data from the comparator.
Claim 9
Dependent Claim
64 words
The delay locked loop of claim 1 wherein the determinator generates a charge control signal to charge the capacitor if a 1 a 2 . . . ā n +a 1 . . . ā n−1 =1, wherein a 1 , a 2 , a 3 , . . . , a n−1 , a n are binary digital output data from the comparator.
Claim 10
Dependent Claim
75 words
The delay locked loop of claim 1 wherein the determinator generates a charge and discharge control signal to charge/discharge the capacitor if [(a 1 a 2 . . . a n )+(a 1 a 2 . . . ā n +a 1 . . . ā n−1 )]=1, wherein a 1 , a 2 , a 3 , . . . , a n−1 , a n are binary digital output data from the comparator.
Claim 11
Dependent Claim
52 words
The delay locked loop of claim 1 wherein the delay cell further comprises: two or more transistors connected in series; a current source connected between a source and a drain of each of the transistors; and a capacitor connected between a common point of the two or more transistors and a ground.
Claim 12
Independent Claim
114 words
A method for a delay locked loop for false lock protection comprising: sending a first signal from a reference clock; delaying the first signal using a delay line and sending a second signal to an output clock; detecting a phase, using a phase detector, in the first signal and the second signal; comparing an order of a rising edge of the second signal with a rising edge of the first signal and generating output data; determining a range to be associated with the rising edge of the second signal, with regard to the reference clock; and controlling the delay line using the phase detector and the output data from the comparing and the range.
Claim 13
Independent Claim
114 words
A method for a delay locked loop for false lock protection comprising: sending a first signal from a reference clock; delaying the first signal using a delay line and sending a second signal to an output clock; detecting a phase, using a phase detector, in the first signal and the second signal; comparing an order of a rising edge of the second signal with a rising edge of the first signal and generating output data; determining a range to be associated with the rising edge of the second signal, with regard to the reference clock; and controlling the delay line using the phase detector and the output data from the comparing and the range.
References Cited (Backward Citations)
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