High frequency circuit using high output amplifier cell block and low output amplifier cell block

Claim 2

A high frequency circuit, comprising: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signals; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted.

Claim 3

The high frequency circuit of claim 1 , wherein the high output amplifier cell block and the low output amplifier cell block are controlled by control voltages to put either one of the high output amplifier cell block and the low output amplifier cell block in an amplification operation state and another one of the high output amplifier cell block and the low output amplifier cell block in a high impedance state.

Claim 4

The high frequency circuit of claim 2 , wherein the first and second connection units are formed by passive elements alone and configured to maintain a matching state with respect to the low output amplifier cell block when the high output amplifier cell block is in the high impedance state or a matching state with respect to the high output amplifier cell block when the low output amplifier cell block is in the high impedance state.

Claim 5

The high frequency circuit of claim 1 , further comprising: at least one middle output amplifier cell block configured to amplify the input signals at a time of middle output power, in which the DC power source voltage is supplied in parallel to third amplifier cells and in series to fourth amplifier cells that are connected in parallel AC-wise with respect to the input/output signals.

Claim 6

The high frequency circuit of claim 1 , wherein the DC power source voltage is supplied from an output port side of the second connection unit.

Claim 7

The high frequency circuit of claim 1 , wherein a common control voltage for controlling the high output amplifier cell block and the low output amplifier cell block is supplied from an input port side of the first connection unit.

Claim 8

The high frequency circuit of claim 1 , wherein the high output amplifier cell block and the low output amplifier cell block are mounted on separate semiconductor chips.

Claim 9

The high frequency circuit of claim 1 , wherein the high output amplifier cell block and the low output amplifier cell block are mounted on a single semiconductor chip.

Claim 10

The high frequency circuit of claim 8 , wherein the first amplifier cells and the second amplifier cells are arranged in a distributed pattern over the single semiconductor chip.

Claim 11

The high frequency circuit of claim 1 , wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by forming the first and second connection units asymmetrically with respect to the high output amplifier cell block and the low output amplifier cell block.

Claim 12

The high frequency circuit of claim 1 , wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by using different transistor sizes for the high output amplifier cell block and the low output amplifier cell block.

Claim 13

The high frequency circuit of claim 1 , wherein source and load impedances of each of the high output amplifier cell block and the low output amplifier cell block are fine tuned by arranging the first amplifier cells and the second amplifier cells at different distances from matching circuits to be connected at an input side of the first connection unit and an output side of the second connection unit.

Claim 14

A communication device, comprising: at least one antenna configured to transmit or receive radio signals; at least one power amplifier configured to amplify the radio signals to be transmitted or received by the at least one antenna, including a high frequency circuit formed by: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signal; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted; and a control unit configured to control the high output amplifier cell block and the low output amplifier cell block by putting either one of the high output amplifier cell block and the low output amplifier cell block in an amplification operation state and another one of the high output amplifier cell block and the low output amplifier cell block in a high impedance state.

Claim 15

A communication device, comprising: at least one antenna configured to transmit or receive radio signals; at least one power amplifier configured to amplify the radio signals to be transmitted or received by the at least one antenna, including a high frequency circuit formed by: a high output amplifier cell block configured to amplify input signals at a time of high output power, in which a DC power source voltage is supplied in parallel to first amplifier cells that are connected in parallel AC-wise with respect to input/output signal; a low output amplifier cell block configured to amplify the input signals at a time of low output power, in which the DC power source voltage is supplied in series to second amplifier cells that are connected in parallel AC-wise with respect to the input/output signals; a first connection unit configured to connect input sides of the high output amplifier cell block and the low output amplifier cell block with an input terminal from which the input signals are entered; and a second connection unit configured to connect output sides of the high output amplifier cell block and the low output amplifier cell block with an output terminal to which output signals are outputted; and a control unit configured to control the high output amplifier cell block and the low output amplifier cell block by putting either one of the high output amplifier cell block and the low output amplifier cell block in an amplification operation state and another one of the high output amplifier cell block and the low output amplifier cell block in a high impedance state.

Claim 16

The communication device of claim 13 , wherein the at least one power amplifier includes a first power amplifier configured to amplify the radio signals to be transmitted from the at least one antenna, and a second power amplifier configured to amplify the radio signals received by the at least one antenna.