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US6794764B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Charge-trapping memory arrays resistant to damage from contact hole information

Assignee: AMD US Holdings Inc
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Filing: 2003-03-05
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Granted: 2004-09-21
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Expires: 2023-03-05
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Abstract

Abstract The present invention relates to a memory array comprising a substrate and a plurality of bitlines having contacts and a plurality of wordlines intersecting the bitlines. A protective spacer is used to separate the bitline contacts from the wordlines adjacent to the bitline contacts to prevent damage caused during the formation of the bitline contacts. The present invention also relates to a method of forming the memory array.

Inventors

  • 👤 Tazrien Kamal
  • 👤 Mark T. Ramsbey
  • 👤 Hidehiko Shiraiwa
  • 👤 Fred T K Cheung

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 05:11
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; H10B69/00; H10W; H10W72/00; H10W72/071; H10W72/075; H10W72/90; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/751; H10W90/756; Y; Y10; Y10S; Y10S257/00; Y10S257/90

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 60 words
A memory array comprising: a substrate; a plurality of bitlines having contacts; a plurality of memory cells, each memory cell located between two bitlines and comprising a charge-trapping dielectric material formed over the substrate; a plurality of wordlines formed over the charge-trapping dielectric material; at least one spacer between the bitlines contacts and the wordline adjacent to the bitline contacts.
Claim 2
Dependent Claim 60 words
A memory array comprising: a substrate; a plurality of bitlines having contacts; a plurality of memory cells, each memory cell located between two bitlines and comprising a charge-trapping dielectric material formed over the substrate; a plurality of wordlines formed over the charge-trapping dielectric material; at least one spacer between the bitlines contacts and the wordline adjacent to the bitline contacts.
Claim 3
Dependent Claim 39 words
The memory array of claim 1 wherein the charge-trapping dielectric material comprises: a bottom dielectric layer formed over the substrate; a charge-trapping layer formed over the bottom dielectric layer; and a top dielectric layer formed over the charge-trapping layer.
Claim 4
Dependent Claim 39 words
The memory array of claim 1 wherein the charge-trapping dielectric material comprises: a bottom oxide layer formed over the substrate; a nitride layer formed over the bottom oxide layer; and a top oxide layer formed over the nitride layer.
Claim 5
Dependent Claim 19 words
The memory array of claim 1 wherein the at least one spacer is formed over the top dielectric layer.
Claim 6
Dependent Claim 21 words
The memory array of claim 1 wherein a spacer separates the edge wordline from the contacts of more than one bitline.
Claim 7
Dependent Claim 19 words
The memory array of claim 1 wherein the spacers are have a stoichiometry of Si 3 N 4 .
Claim 8
Dependent Claim 18 words
The memory array of claim 1 wherein the spacers range from about 250 angstroms to about 1300 angstroms.
Claim 9
Dependent Claim 18 words
The memory array of claim 1 wherein the spacers range from about 750 angstroms to about 1200 angstroms.
Claim 10
Dependent Claim 18 words
The method array of claim 1 wherein the spacer is about the same height as the wordline material.
Claim 11
Dependent Claim 16 words
The memory array of claim 1 wherein the spacers are formed over the top dielectric layer.
Claim 12
Dependent Claim 21 words
The memory array of claim 1 wherein the spacers comprise one or more of: silicon nitride, silicon rich nitride, and SiON.
Claim 13
Dependent Claim 19 words
The memory array of claim 1 wherein the spacers are have a stoichiometry of Si 3 N 4 .
Claim 14
Dependent Claim 15 words
The memory array of claim 1 wherein the charge-trapping memory cells are dual-bit memory cells.
Claim 15
Dependent Claim 16 words
The memory array of claim 1 wherein the charge-trapping memory cells are floating gate memory cells.
Claim 16
Dependent Claim 28 words
The memory array of claim 1 wherein the array is an memory block having a size of 2 (n+1) K where n is an integer greater than 0.
Claim 17
Dependent Claim 15 words
The memory array of claim 15 wherein the array is a plurality connected memory blocks.
Claim 18
Independent Claim 60 words
A method for forming a memory array comprising the steps of: providing a substrate; forming a charge-trapping dielectric material over the substrate; forming a plurality of bitlines having contact locations; forming wordlines over the charge-trapping dielectric material; and forming spacers between the bitline contact locations and wordlines adjacent to bitline contact locations; forming bitline contacts at the bitline contact locations.
Claim 19
Independent Claim 60 words
A method for forming a memory array comprising the steps of: providing a substrate; forming a charge-trapping dielectric material over the substrate; forming a plurality of bitlines having contact locations; forming wordlines over the charge-trapping dielectric material; and forming spacers between the bitline contact locations and wordlines adjacent to bitline contact locations; forming bitline contacts at the bitline contact locations.
Claim 20
Dependent Claim 47 words
The method of claim 17 wherein the step of forming a charge-trapping dielectric material comprises the steps of: forming a bottom dielectric layer above the substrate; forming a charge-trapping layer formed over the bottom dielectric layer; and forming a top dielectric layer over the charge storage layer.
Claim 21
Dependent Claim 22 words
The method of claim 17 further comprising the step of forming an etch stop layer above the spacer and the gate electrode.
Claim 22
Dependent Claim 18 words
The method of claim 19 wherein the etch stop layers are formed prior to forming the bitline contacts.

References Cited (Backward Citations)

US6349052B1 Cited
US6275414B1 Cited
EP1263050A1 Cited
US20030109104A1 Cited
US6420237B1 Cited
US20030075738A1 Cited
US6524913B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2007-09-21 2008-03-22 2008-09-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2011-09-21 2012-03-22 2012-09-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2015-09-21 2016-03-22 2016-09-21 $7700.00 Window Closed / Lapsed

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