US6420237B1
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US
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Method of manufacturing twin bit cell flash memory device
Assignee: Macronix International Co Ltd
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Filing: 2001-10-22
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Granted: 2002-07-16
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Expires: 2021-10-22
Abstract
Abstract The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si 1−x Ge x ,x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.
Inventors
- 👤 Kent Kuohua Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:38
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0458; H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
111 words
A method for fabricating a twin bit cell flash memory device, the method comprising: providing a substrate; forming a gate oxide layer on the surface of the silicon substrate; forming a polysilicon germanium layer on the surface of the gate oxide layer; performing an ion implantation process to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure; forming a dielectric layer on the surface of the polysilicon germanium layer; forming a patterned floating gate on the surface of the dielectric layer; and forming a control gate located over the floating gate.
Claim 2
Independent Claim
111 words
A method for fabricating a twin bit cell flash memory device, the method comprising: providing a substrate; forming a gate oxide layer on the surface of the silicon substrate; forming a polysilicon germanium layer on the surface of the gate oxide layer; performing an ion implantation process to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure; forming a dielectric layer on the surface of the polysilicon germanium layer; forming a patterned floating gate on the surface of the dielectric layer; and forming a control gate located over the floating gate.
Claim 3
Dependent Claim
42 words
The method of claim 1 wherein the polysilicon germanium layer is formed by performing a chemical vapor deposition (CVD) process using silane (SiH 4 ), germane(GeH 4 ) and hydrogen as reacting gases at a temperature of 450° C. to 620° C.
Claim 4
Dependent Claim
38 words
The method of claim 1 wherein another high temperature annealing process performed at a temperature of 950° C. to 1150° C. diffuses the doped ions formed in the ion implantation process so as to form the insulating region.
Claim 5
Dependent Claim
21 words
The method of claim 1 wherein the chemical composition of the polysilicon germanium layer is Si 1−x Ge x , x=0.05˜1.0.
Claim 6
Dependent Claim
49 words
The method of claim 1 wherein after the formation of the floating gate, an ion implantation process and a thermal oxidation process are performed to form bit lines of the memory device and a field oxide layer on the surface of the bit line to separate each floating gate.
Claim 7
Dependent Claim
24 words
The method of claim 5 wherein the thermal oxidation process also forms an oxide layer on the exposed side walls of each conductive region.
Claim 8
Independent Claim
111 words
A method for fabricating a twin bit cell flash memory device, the method comprising: providing a substrate; forming a gate oxide layer on the surface of the silicon substrate; forming a polysilicon germanium layer on the surface of the gate oxide layer; forming a dielectric layer on the surface of the polysilicon germanium layer; performing an ion implantation process to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure; forming a patterned floating gate on the surface of the dielectric layer; and forming a control gate located over the floating gate.
Claim 9
Independent Claim
111 words
A method for fabricating a twin bit cell flash memory device, the method comprising: providing a substrate; forming a gate oxide layer on the surface of the silicon substrate; forming a polysilicon germanium layer on the surface of the gate oxide layer; forming a dielectric layer on the surface of the polysilicon germanium layer; performing an ion implantation process to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure; forming a patterned floating gate on the surface of the dielectric layer; and forming a control gate located over the floating gate.
Claim 10
Dependent Claim
21 words
The method of claim 7 wherein the chemical composition of the polysilicon germanium layer is Si 1−x Ge x , x=0.05˜1.0.
Claim 11
Dependent Claim
42 words
The method of claim 7 wherein the polysilicon germanium layer is formed by performing a chemical vapor deposition (CVD) process using silane (SiH 4 ), germane(GeH 4 ) and hydrogen as reacting gases at a temperature of 450° C. to 620° C.
Claim 12
Dependent Claim
38 words
The method of claim 7 wherein another high temperature annealing process performed at a temperature of 950° C. to 1150° C. diffuses the doped ions formed in the ion implantation process so as to form the insulating region.
Claim 13
Dependent Claim
49 words
The method of claim 7 wherein after the formation of the floating gate, an ion implantation process and a thermal oxidation process are performed to form bit lines of the memory device and a field oxide layer on the surface of the bit line to separate each floating gate.
Claim 14
Dependent Claim
24 words
The method of claim 11 wherein the thermal oxidation process also forms an oxide layer on the exposed side walls of each conductive region.
Claim 15
Independent Claim
145 words
A method for fabricating a twin bit cell flash memory device, the method comprising: providing a substrate; forming a gate oxide layer on the surface of the silicon substrate; forming a polysilicon germanium layer on the surface of the gate oxide layer; performing an ion implantation process to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure; forming a patterned floating gate on the polysilicon germanium layer; performing an ion implantation process to form a plurality of doped areas in the silicon substrate, which function as bit lines of the memory device; performing a thermal oxidation process to form a field oxide layer on the surface of the bit line to separate each floating gate; and forming a control gate located over the floating gate.
Claim 16
Independent Claim
145 words
A method for fabricating a twin bit cell flash memory device, the method comprising: providing a substrate; forming a gate oxide layer on the surface of the silicon substrate; forming a polysilicon germanium layer on the surface of the gate oxide layer; performing an ion implantation process to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure; forming a patterned floating gate on the polysilicon germanium layer; performing an ion implantation process to form a plurality of doped areas in the silicon substrate, which function as bit lines of the memory device; performing a thermal oxidation process to form a field oxide layer on the surface of the bit line to separate each floating gate; and forming a control gate located over the floating gate.
Claim 17
Dependent Claim
21 words
The method of claim 13 wherein the chemical composition of the polysilicon germanium layer is Si 1−x Ge x , x=0.05˜1.0.
Claim 18
Dependent Claim
42 words
The method of claim 13 wherein the polysilicon germanium layer is formed by performing a chemical vapor deposition (CVD) process using silane (SiH 4 ), germane(GeH 4 ) and hydrogen as reacting gases at a temperature of 450° C. to 620° C.
Claim 19
Dependent Claim
38 words
The method of claim 13 wherein another high temperature annealing process performed at a temperature of 950° C. to 1150° C. diffuses the doped ions formed in the ion implantation process so as to form the insulating region.
Claim 20
Dependent Claim
24 words
The method of claim 13 wherein the thermal oxidation process also forms an oxide layer on the exposed side walls of each conductive region.
References Cited (Backward Citations)
US6214681B1
Cited
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