Patent US6781861B2 successfully refreshed from Google Patents.
US6781861B2
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Method and apparatus for determining digital delay line entry point
Assignee: Round Rock Research LLC
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Filing: 2003-04-28
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Granted: 2004-08-24
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Expires: 2023-04-28
Abstract
Abstract A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.
Inventors
- 👤 Tyler J. Gomm
- 👤 Aaron M. Schoenfeld
- 👤 Travis E. Dirkes
- 👤 Ross E. Dermott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:20
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C7/22; G11C7/222; G11C2207/00; G11C2207/22; G11C2207/2254
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
77 words
A method of producing a plurality of memory devices comprising the acts of: electrically testing a portion of the plurality of memory devices, each of the memory devices comprising a delay locked loop (DLL) circuit; characterizing the DLL circuits based on the electrical testing of the portion of the plurality of memory devices; producing characterization data corresponding to a locking point of the DLL circuit; and redesigning the plurality of memory devices based on the characterization data.
Claim 2
Independent Claim
77 words
A method of producing a plurality of memory devices comprising the acts of: electrically testing a portion of the plurality of memory devices, each of the memory devices comprising a delay locked loop (DLL) circuit; characterizing the DLL circuits based on the electrical testing of the portion of the plurality of memory devices; producing characterization data corresponding to a locking point of the DLL circuit; and redesigning the plurality of memory devices based on the characterization data.
Claim 3
Dependent Claim
32 words
The method of producing a plurality of memory devices, as set forth in claim 1 , wherein the act of electrically testing the memory devices is repeated over a variety of conditions.
Claim 4
Dependent Claim
21 words
The method of producing a plurality of memory devices, as set forth in claim 2 , wherein the conditions comprise temperatures.
Claim 5
Dependent Claim
21 words
The method of producing a plurality of memory devices, as set forth in claim 2 , wherein the conditions comprise voltages.
Claim 6
Independent Claim
171 words
A method of manufacturing a memory device comprising: providing a delay locked loop (DLL) circuit, wherein providing the DLL circuit comprises: providing a digital delay line comprising a plurality of delay elements configured to receive an input signal and to produce an output signal, and wherein the input signal has a first phase and the output signal has a second phase; providing a phase detector configured to receive the input signal and the output signal and further configured to compare the first phase and the second phase and to produce a shift command output based on the comparison between the first phase and the second phase; and providing a shift register coupled between the phase detector and the digital delay line and configured to shift the input signal by an amount of time equivalent to one delay element in response to the shift command output from the phase detector; and providing a counter coupled to the DLL circuit and configured to track an amount of added delay in the DLL circuit.
Claim 7
Independent Claim
171 words
A method of manufacturing a memory device comprising: providing a delay locked loop (DLL) circuit, wherein providing the DLL circuit comprises: providing a digital delay line comprising a plurality of delay elements configured to receive an input signal and to produce an output signal, and wherein the input signal has a first phase and the output signal has a second phase; providing a phase detector configured to receive the input signal and the output signal and further configured to compare the first phase and the second phase and to produce a shift command output based on the comparison between the first phase and the second phase; and providing a shift register coupled between the phase detector and the digital delay line and configured to shift the input signal by an amount of time equivalent to one delay element in response to the shift command output from the phase detector; and providing a counter coupled to the DLL circuit and configured to track an amount of added delay in the DLL circuit.
Claim 8
Dependent Claim
64 words
The method of manufacturing the memory device, as set forth in claim 5 , wherein providing a digital delay line comprising a plurality of delay elements configured to receive an input signal comprises providing providing a digital delay line comprising a plurality of delay elements configured to receive a clock signal, the clock signal being generated by a device external to the memory device.
Claim 9
Dependent Claim
23 words
The method of manufacturing the memory device, as set forth in claim 5 , wherein the clock signal comprises a buffered clock signal.
Claim 10
Dependent Claim
45 words
The method of manufacturing the memory device, as set forth in claim 5 , wherein providing the DLL circuit providing a feedback delay line and wherein the output signal is delivered from the digital delay line to the phase detector through the feedback delay line.
Claim 11
Dependent Claim
57 words
The method of manufacturing the memory device, as set forth in claim 5 , wherein providing the shift register and providing the counter comprises providing a shift register and a counter, wherein each of the shift register and the counter is configured to be initialized to a known state when the DLL circuit receives a RESET command.
Claim 12
Dependent Claim
44 words
The method of manufacturing the memory device, as set forth in claim 5 , wherein providing the DLL circuit comprises providing a DLL circuit configured to achieve a locking point of the DLL circuit when the first phase is equal to the second phase.
Claim 13
Dependent Claim
33 words
The method of manufacturing the memory device, as set forth in claim 10 , wherein the locking point of the DLL circuit corresponds to an amount of added delay in the input signal.
Claim 14
Dependent Claim
32 words
The method of manufacturing the memory device, as set forth in claim 11 , wherein the amount of added delay is correlative to a number of delay elements in the delay line.
Claim 15
Dependent Claim
53 words
The method of manufacturing the memory device, as set forth in claim 12 , wherein providing the counter comprises providing a counter configured to track the amount of added delay by counting the number of delay elements used to add the amount of delay corresponding to the locking point of the DLL circuit.
Claim 16
Dependent Claim
49 words
The method of manufacturing the memory device, as set forth in claim 13 , comprising providing a probe pad on the memory device, wherein the probe pad is configured to receive an output signal from the counter, the output signal comprising information corresponding to the amount of added delay.
Claim 17
Dependent Claim
49 words
The method of manufacturing the memory device, as set forth in claim 13 , comprising providing a serializer on the memory device, wherein the serializer is configured to receive and store an output signal from the counter, the output signal comprising information corresponding to the amount of added delay.
Claim 18
Dependent Claim
91 words
The method of manufacturing the memory device, as set forth in claim 15 , comprising providing a multiplexor on the memory device, wherein the multiplexor is configured to receive an output signal from the serializer corresponding to the amount of added delay and further configured to toggle between a test mode of operation in which the output signal from the counter is passed through the multiplexor and to additional system components and a normal mode of operation in which memory data is passed through the multiplexor and to additional system components.
Claim 19
Independent Claim
99 words
A method of manufacturing a memory device comprising; providing a delay locked loop (DLL) circuit, wherein providing the DLL circuit comprises: providing a digital delay line having an input and an output and comprising a plurality of delay elements, each delay element having a corresponding entry point; providing a phase detector coupled to the input and the output of the digital delay line; and providing a shift register coupled between the phase detector and the digital delay line and configured to shift to each of the delay element entry points; and providing a counter coupled to the DLL circuit.
Claim 20
Independent Claim
99 words
A method of manufacturing a memory device comprising; providing a delay locked loop (DLL) circuit, wherein providing the DLL circuit comprises: providing a digital delay line having an input and an output and comprising a plurality of delay elements, each delay element having a corresponding entry point; providing a phase detector coupled to the input and the output of the digital delay line; and providing a shift register coupled between the phase detector and the digital delay line and configured to shift to each of the delay element entry points; and providing a counter coupled to the DLL circuit.
Claim 21
Dependent Claim
53 words
The method of manufacturing a memory device, as set forth in claim 17 , wherein providing the digital delay line comprises providing a digital delay line configured to receive an input signal delivered to the input of the digital delay line, the input being generated by a device external to the memory device.
Claim 22
Dependent Claim
21 words
The method of manufacturing a memory device, as set forth in claim 18 , wherein input signal comprises a clock signal.
Claim 23
Dependent Claim
54 words
The method of manufacturing a memory device, as set forth in claim 18 , wherein providing the DLL circuit comprises providing a DLL circuit configured to achieve a locking point of the DLL circuit when the phase at the input signal is equal to the phase of the output of the digital delay line.
Claim 24
Dependent Claim
35 words
The method of manufacturing a memory device, as set forth claim 20 , wherein the locking point of the DLL circuit corresponds to an amount of delay added to the phase of the input signal.
Claim 25
Dependent Claim
32 words
The method of manufacturing a memory device, as set forth in claim 21 , wherein the amount of delay added is correlative to a number of delay elements in the delay line.
Claim 26
Dependent Claim
53 words
The method of manufacturing the memory device, as set forth in claim 22 , wherein providing the counter comprises providing a counter configured to track the amount of added delay by counting the number of delay elements used to add the amount of delay corresponding to the locking point of the DLL circuit.
Claim 27
Dependent Claim
49 words
The method of manufacturing the memory device, as set forth in claim 23 , comprising providing a probe pad on the memory device, wherein the probe pad is configured to receive an output signal from the counter, the output signal comprising information corresponding to the amount of added delay.
Claim 28
Dependent Claim
49 words
The method of manufacturing the memory device, as set forth in claim 23 , comprising providing a serializer on the memory device, wherein the serializer is configured to receive and store an output signal from the counter, the output signal comprising information corresponding to the amount of added delay.
Claim 29
Dependent Claim
46 words
The method of manufacturing the memory device, as set forth in claim 17 , wherein providing the DLL circuit comprises providing a feedback delay line and wherein the output signal is delivered from the digital delay line to the phase detector through the feedback delay line.
Claim 30
Dependent Claim
57 words
The method of manufacturing the memory device, as set forth in claim 17 , wherein providing the shift register and providing the counter comprises providing a shift register and a counter, wherein each of the shift register and the counter is configured to be initialized to a known state when the DLL circuit receives a RESET command.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-08-24 | 2008-02-23 | 2008-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-08-24 | 2012-02-23 | 2012-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-08-24 | 2016-02-23 | 2016-08-24 | $7700.00 | Window Closed / Lapsed |