NROM memory circuit with recessed bitline

Claim 2

Integrated memory circuit, comprising: a semiconductor substrate having a semiconductor substrate surface plain; an array of memory cells formed on the substrate, the array of memory cells including bit lines and word lines, the bit lines and word lines connecting the memory cells, the bit lines being formed of a material different from a material of the substrate and having a bit line top plane; a controlling circuit formed on the substrate for controlling the array of memory cells, wherein the bit lines and the word lines extend into the controlling circuit; and wherein the bit lines are recessed with respect to the semiconductor substrate surface plane such that a difference between the bit line top plane and the semiconductor substrate surface plane is smaller than 50 nanometers.

Claim 3

Integrated memory circuit in accordance with claim 1 , wherein a memory cell includes: a source region connected to a bit line; a drain region connected to a neighboring bit line; a groove-shaped channel region formed between the source region and the drain region, the channel region including a lower insulating layer, a storing layer and an upper insulating layer.

Claim 4

Integrated memory circuit in accordance with claim 2 , in which the source region of a memory cell is connected to a first bit line, in which the drain region of the memory cell is connected to a second neighboring bit line, in which a word line of the memory cell crosses the first bit line and the second bit line, the word line being positioned above the first bit line and the second bit line.

Claim 5

Integrated memory circuit in accordance with claim 3 , in which the memory cell includes two bit storing positions that are located at crossing regions between the word line and the first bit line or the second bit line.

Claim 6

Integrated memory circuit in accordance with claim 2 , in which the upper and the lower insulating region are formed of oxide, and the storing region is formed of nitride.

Claim 7

Integrated memory circuit in accordance with claim 2 , in which the bit line includes a lower polysilicon layer, a silicide layer on the lower polysilicon layer and a fill oxide layer above the silicide layer.

Claim 8

Integrated memory circuit in accordance with claim 6 , in which the lower insulating layer, the storing layer and the upper insulating layer are also provided on the fill oxide layer of the bit line.

Claim 9

Integrated memory circuit in accordance with claim 1 , in which a word line includes a lower polysilicon layer, a silicide layer above the polysilicon layer and an antireflective coating layer above the silicide layer.

Claim 10

Integrated memory cell in accordance with claim 1 , in which the word line includes a layer of polysilicon, a layer of tungsten nitride, a layer of tungsten and, above the layer of tungsten, a hard mask.

Claim 11

Integrated memory cell in accordance with claim 1 , in which trenches filled with insulating material are provided between adjacent word lines, the trenches extending deeper into the semiconductor substrate than a groove-shaped channel region of a memory cell.

Claim 12

Integrated memory cell in accordance with claim 1 , in which the bit lines are arranged in recesses formed in trenches, and extend above the trenches.

Claim 13

Integrated memory cell in accordance with claim 1 , in which the word lines have a word line bottom plane, where the difference between the word line bottom plane and the semiconductor surface plane is smaller than the predetermined value.

Claim 14

Integrated memory cell in accordance with claim 1 , in which distances between two neighboring bit lines or two neighboring word lines are smaller than 150 nanometers.

Claim 15

Method according to claim 13 , in which the bit line recesses and the bit lines are designed such that the difference between a bit line top plane and a substrate surface plane is smaller than a predetermined value.

Claim 16

Method in accordance with claim 13 , in which the step of providing a substrate includes providing an oxide layer on a substrate surface and a nitride layer above the oxide layer; in which the step of forming bit line recesses includes the following substeps: lithographically defining the bit line recesses; selectively etching using the oxide layer as an etch stop; selectively etching using nitride as an etch stop until a predetermined recess depth is obtained.

Claim 17

Method in accordance with claim 15 , in which the step of forming bit lines includes the following substeps: forming side wall spacers in the bit line recesses; forming a layer of polysilicon in the bit line recesses; forming a metal-silicon compound layer or a metal layer on the layer of polysilicon using a silicide method; and filling remaining gaps of the bit line recesses with oxide.

Claim 18

Method in accordance with claim 13 , in which a step of implanting is performed before the step of forming bit lines.

Claim 19

Method in accordance with claim 17 , in which the metal of the silicon/metal compound is Co or Tungsten.

Claim 20

Method in accordance with claim 13 , wherein in the step of forming bit lines, metallized bit lines are produced.

Claim 21

Method in accordance with claim 13 , in which the step of forming gate regions includes the following substeps: lithographically removing a nitride layer on the semiconductor substrate within the memory cell array; selectively etching grooves into the semiconductor substrate using a top oxide layer of the bit lines as an etch stop; and forming an oxide-nitride-oxide layer in the grooves.

Claim 22

Method in accordance with claim 13 , in which the step of forming word lines includes the following substeps: filling remaining grooves in the gate regions with polysilicon; proving a metal-silicon compound layer on the polysilicon layer and hard mask on the metal-silicon compound layer; and lithographically defining the word lines and etching the word lines using an oxide layer on the bit lines as an etch stop.

Claim 23

Integrated memory circuit in accordance with claim 13 , further comprising the following step: forming the controlling circuit for controlling the array of memory cells as a CMOS circuit.

Claim 24

Integrated memory circuit in accordance with claim 13 , in which the step of providing a semiconductor substrate includes a step of forming a shallow trench insulation between adjacent word lines.

Claim 25

Integrated memory cell in accordance with claim 1 , in which the predetermined value is defined by a lithography technique performed for patterning the word lines.

Claim 26

Method in accordance with claim 24 , in which the predetermined value is 50 nanometers or smaller.

Claim 27

Method of forming an integrated memory circuit, the method comprising: providing a semiconductor substrate; forming bit line recesses in the substrate; forming bit lines in the recesses, wherein two adjacent bit lines are connected to a source and a drain region of a memory cell in an array of memory cells; forming gate regions of the memory cells; and forming word lines on the gate regions of the memory cells and gate structures of transistors in a control circuit for the array of memory cells, the word lines and the bit lines extending into the control circuit.

Claim 28

Method of forming an integrated memory circuit, the method comprising: providing a semiconductor substrate; forming bit line recesses in the substrate; forming bit lines in the recesses, wherein two adjacent bit lines are connected to a source and a drain region of a memory cell in an array of memory cells; forming gate regions of the memory cells; and forming word lines on the gate regions of the memory cells and gate structures of transistors in a control circuit for the array of memory cells, the word lines and the bit lines extending into the control circuit.

Claim 29

An integrated memory circuit, comprising: a semiconductor substrate having a semiconductor substrate surface plain; memory cells including a source region connected to a bit line, a drain region connected to a neighboring bit line, a groove-shaped channel region formed between the source region and the drain region, the channel region including a lower insulating layer, a storm layer and an upper insulating layer; an array of the memory cells being formed on the substrate, the array of the memory cells including bit lines and word lines, the bit lines and word lines connecting the memory cells, the bit lines being formed of a material different from a material of the substrate and having a bit line top plane, a lower polysilicon layer, a suicide layer on the lower polysilicon layer and a fill oxide layer above the silicide layer; a controlling circuit formed on the substrate for controlling the array of memory cells, wherein the bit lines and the word lines extend into the controlling circuit; and wherein the bit lines are recessed with respect to the semiconductor substrate surface plane such that a difference between the bit line top plane and the semiconductor substrate surface plane is smaller than a predetermined value.

Claim 30

An integrated memory circuit, comprising: a semiconductor substrate having a semiconductor substrate surface plain; memory cells including a source region connected to a bit line, a drain region connected to a neighboring bit line, a groove-shaped channel region formed between the source region and the drain region, the channel region including a lower insulating layer, a storm layer and an upper insulating layer; an array of the memory cells being formed on the substrate, the array of the memory cells including bit lines and word lines, the bit lines and word lines connecting the memory cells, the bit lines being formed of a material different from a material of the substrate and having a bit line top plane, a lower polysilicon layer, a suicide layer on the lower polysilicon layer and a fill oxide layer above the silicide layer; a controlling circuit formed on the substrate for controlling the array of memory cells, wherein the bit lines and the word lines extend into the controlling circuit; and wherein the bit lines are recessed with respect to the semiconductor substrate surface plane such that a difference between the bit line top plane and the semiconductor substrate surface plane is smaller than a predetermined value.

Claim 31

Integrated memory circuit in accordance with claim 27 , in which the source region of a memory cell is connected to a first bit line, in which the drain region of the memory cell is connected to a second neighboring bit line, in which a word line of the memory cell crosses the first bit line and the second bit line, the word line being positioned above the first bit line and the second bit line.

Claim 32

Integrated memory circuit in accordance with claim 28 , in which the memory cell includes two bit storing positions that are located at crossing regions between the word line and the first bit line or the second bit line.

Claim 33

Integrated memory circuit in accordance with claim 27 , in which the upper and the lower insulating region are formed of oxide, and the storing region is formed of nitride.

Claim 34

Integrated memory circuit in accordance with claim 27 , in which the lower insulating layer, the storing layer and the upper insulating layer are also provided on the fill oxide layer of the bit line.

Claim 35

Integrated memo circuit in accordance with claim 27 , in which a word line includes a lower polysilicon layer, a silicide layer above the polysilicon layer and an antireflective coating layer above the silicide layer.

Claim 36

Integrated memory cell in accordance with claim 27 , in which the word line includes a layer of polysilicon, a layer of tungsten nitride, a layer of tungsten and, above the layer of tungsten, a hard mask.

Claim 37

Integrated memory circuit, comprising: a semiconductor substrate having a semiconductor substrate surface plain; an array of memory cells formed on the substrate, the array of memory cells including bit lines and word lines, the bit lines and word lines connecting the memory cells, the bit lines being formed of a material different from a material of the substrate and having a bit line top plane; trenches filled with insulating material are provided between adjacent word lines, the trenches extending deeper into the semiconductor substrate than a groove-shaped channel region of a memory cell; a controlling circuit formed on the substrate for controlling the array of memory cells, wherein the bit lines and the word lines extend into the controlling circuit; and wherein the bit lines are recessed with respect to the semiconductor substrate surface plane such that a difference between the bit line top plane and the semiconductor substrate surface plane is smaller than a predetermined value.

Claim 38

Integrated memory circuit, comprising: a semiconductor substrate having a semiconductor substrate surface plain; an array of memory cells formed on the substrate, the array of memory cells including bit lines and word lines, the bit lines and word lines connecting the memory cells, the bit lines being formed of a material different from a material of the substrate and having a bit line top plane; trenches filled with insulating material are provided between adjacent word lines, the trenches extending deeper into the semiconductor substrate than a groove-shaped channel region of a memory cell; a controlling circuit formed on the substrate for controlling the array of memory cells, wherein the bit lines and the word lines extend into the controlling circuit; and wherein the bit lines are recessed with respect to the semiconductor substrate surface plane such that a difference between the bit line top plane and the semiconductor substrate surface plane is smaller than a predetermined value.

Claim 39

Integrated memory circuit in accordance with claim 34 , wherein a memory cell includes a source region connected to a bit line, a drain region connected to a neighboring bit line, and the groove-shape channel region is formed between the source region and the drain region, the channel region including a lower insulating layer, a storing layer and an upper insulating layer.

Claim 40

Integrated memory circuit in accordance with claim 35 , in which the source region of a memory cell is connected to a first bit line, in which the drain region of the memory cell is connected to a second neighboring bit line, in which a word line of the memory cell crosses the first bit line and the second bit line, the word line being positioned above the first bit line and the second bit line.

Claim 41

Integrated memory circuit in accordance with claim 36 , in which the memory cell includes two bit storing positions that are located at crossing regions between the word line and the first bit, line or the second bit line.

Claim 42

Integrated memory circuit in accordance with claim 34 , in which the upper and the lower insulating region are formed of oxide, and the storing region is formed of nitride.

Claim 43

Integrated memory circuit in accordance with claim 34 , in which the bit line includes a lower polysilicon layer, a suicide layer on the lower polysilicon layer and a fill oxide layer above the silicide layer.

Claim 44

Integrated memo circuit in accordance with claim 34 , in which the lower insulating layer, the storing layer and the upper insulating layer are also provided on the fill oxide layer of the bit line.