US6468865B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of simultaneous formation of bitline isolation and periphery oxide
Assignee: Longitude Flash Memory Solutions Ltd
•
Filing: 2000-11-28
•
Granted: 2002-10-22
•
Expires: 2020-11-28
Abstract
Abstract One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.
Inventors
- 👤 Jean Y. Yang
- 👤 Mark T. Ramsbey
- 👤 Hidehiko Shiraiwa
- 👤 Michael A. Van Buskirk
- 👤 David M. Rogers
- 👤 Ravi Sunkavalli
- 👤 Janet Wang
- 👤 Narbeh Derhacobian
- 👤 Yider Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:16
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; H10B69/00
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
116 words
A method of forming a non-volatile semiconductor memory device, comprising: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a first portion of a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; simultaneously forming a bitline isolation over the buried bitlines in the core region and a second portion of the gate dielectric in the periphery region; and forming gates in the core region and the periphery region.
Claim 2
Independent Claim
116 words
A method of forming a non-volatile semiconductor memory device, comprising: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a first portion of a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; simultaneously forming a bitline isolation over the buried bitlines in the core region and a second portion of the gate dielectric in the periphery region; and forming gates in the core region and the periphery region.
Claim 3
Dependent Claim
32 words
The method according to claim 1 , wherein the buried bitlines are formed in the core region after removing at least a portion of the charge trapping dielectric in the periphery region.
Claim 4
Dependent Claim
32 words
The method according to claim 1 , wherein the buried bitlines are formed in the core region before removing at least a portion of the charge trapping dielectric in the periphery region.
Claim 5
Dependent Claim
41 words
The method according to claim 1 , wherein the bitline isolation in the core region and the second portion of the gate dielectric in the periphery region are formed simultaneously by one of wet oxidation, dry oxidation, and rapid thermal oxidation.
Claim 6
Independent Claim
118 words
A method of forming a non-volatile semiconductor memory device, comprising sequentially: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a first portion of a gate dielectric in the periphery region; removing at least a portion of the charge trapping dielectric positioned over subsequently formed buried bitlines in the core region; forming buried bitlines in the core region; simultaneously forming a bitline isolation over the buried bitlines in the core region and a second portion of the gate dielectric in the periphery region; and forming gates in the core region and the periphery region.
Claim 7
Independent Claim
118 words
A method of forming a non-volatile semiconductor memory device, comprising sequentially: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a first portion of a gate dielectric in the periphery region; removing at least a portion of the charge trapping dielectric positioned over subsequently formed buried bitlines in the core region; forming buried bitlines in the core region; simultaneously forming a bitline isolation over the buried bitlines in the core region and a second portion of the gate dielectric in the periphery region; and forming gates in the core region and the periphery region.
Claim 8
Dependent Claim
41 words
The method according to claim 5 , wherein the bitline isolation in the core region and the second portion of the gate dielectric in the periphery region are formed simultaneously by one of wet oxidation, dry oxidation, and rapid thermal oxidation.
Claim 9
Dependent Claim
23 words
The method according to claim 5 , wherein the buried bitlines are formed by implanting at least one of arsenic, boron, and phosphorus.
Claim 10
Dependent Claim
26 words
The method according to claim 5 , wherein the gate dielectric in the periphery region has a thickness from about 30 Å to about 300 Å.
Claim 11
Dependent Claim
32 words
The method according to claim 7 , wherein at least one of arsenic, boron, and phosphorus are implanted at a dosage from about 1×10 14 to about 1×10 16 atoms/cm 2 .
Claim 12
Dependent Claim
31 words
The method according to claim 5 , wherein the charge trapping dielectric comprises an ONO dielectric comprising at least one of a nitrided oxide layer and a silicon rich nitride layer.
Claim 13
Dependent Claim
66 words
The method according to claim 5 , wherein the charge trapping dielectric comprises one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 14
Dependent Claim
22 words
The method according to claim 5 , wherein the bitline isolation has a thickness from about 25 Å to about 300 Å.
Claim 15
Dependent Claim
22 words
The method according to claim 5 , wherein the buried bitlines have a width from about 0.18 μm to about 1 μm.
Claim 16
Dependent Claim
23 words
The method according to claim 5 further comprising performing a blanket threshold implant prior to forming the charge trapping dielectric over the substrate.
Claim 17
Dependent Claim
31 words
The method according to claim 5 further comprising performing a threshold implant after forming the charge trapping dielectric over the substrate and prior to forming buried bitlines in the core region.
Claim 18
Dependent Claim
20 words
The method according to claim 5 further comprising performing a threshold implant after forming buried bitlines in the core region.
Claim 19
Dependent Claim
46 words
The method according to claim 5 , wherein a first region of the gate dielectric in the periphery region has a first thickness and a second region of the gate dielectric in the periphery region has a second thickness that is different from the first thickness.
Claim 20
Independent Claim
113 words
A method of forming a non-volatile semiconductor memory device, comprising: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; removing at least a portion of the charge trapping dielectric in the periphery region thereby exposing portions of the substrate; simultaneously forming a bitline isolation over the buried bitlines in the core region and a gate dielectric over the exposed portions of the substrate in the periphery region; and forming gates in the core region and the periphery region.
Claim 21
Independent Claim
113 words
A method of forming a non-volatile semiconductor memory device, comprising: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; removing at least a portion of the charge trapping dielectric in the periphery region thereby exposing portions of the substrate; simultaneously forming a bitline isolation over the buried bitlines in the core region and a gate dielectric over the exposed portions of the substrate in the periphery region; and forming gates in the core region and the periphery region.
Claim 22
Dependent Claim
22 words
The method according to claim 18 , wherein the bitline isolation has a thickness from about 25 Å to about 300 Å.
Claim 23
Dependent Claim
23 words
The method according to claim 18 , wherein the buried bitlines are formed by implanting at least one of arsenic, boron, and phosphorus.
Claim 24
Dependent Claim
26 words
The method according to claim 18 , wherein the gate dielectric in the periphery region has a thickness from about 30 Å to about 300 Å.
Claim 25
Dependent Claim
32 words
The method according to claim 20 , wherein at least one of arsenic, boron, and phosphorus are implanted at a dosage from about 1×10 14 to about 1×10 16 atoms/cm 2 .
Claim 26
Dependent Claim
32 words
The method according to claim 18 , wherein the gate dielectric in the periphery region and the bitline isolation are formed by one of wet oxidation, dry oxidation, and rapid thermal oxidation.
Claim 27
Dependent Claim
66 words
The method according to claim 18 , wherein the charge trapping dielectric comprises one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 28
Dependent Claim
31 words
The method according to claim 18 , wherein the charge trapping dielectric comprises an ONO dielectric comprising at least one of a nitrided oxide layer and a silicon rich nitride layer.
Claim 29
Dependent Claim
22 words
The method according to claim 18 , wherein the buried bitlines have a width from about 0.18 μm to about 1 μm.
Claim 30
Dependent Claim
23 words
The method according to claim 18 further comprising performing a blanket threshold implant prior to forming the charge trapping dielectric over the substrate.
Claim 31
Dependent Claim
31 words
The method according to claim 18 further comprising performing a threshold implant after forming the charge trapping dielectric over the substrate and prior to forming buried bitlines in the core region.
Claim 32
Dependent Claim
42 words
The method according to claim 18 further comprising performing a threshold implant after forming buried bitlines in the core region and prior to removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region.
Claim 33
Dependent Claim
32 words
The method according to claim 18 , wherein the buried bitlines in the core region are formed after removing at least a portion of the charge trapping dielectric in the core region.
References Cited (Backward Citations)
US4173766A
Cited
US5168334A
Cited
US5349221A
Cited
US5644533A
Cited
US5825686A
Cited
US5768192A
Cited
US5966603A
Cited
US6011725A
Cited
US5963465A
Cited
US6001709A
Cited
US6030871A
Cited
WO1999060631A1
Cited
US6287917B1
Cited
US6117730A
Cited
US6326268B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-21 | 2006-04-22 | 2006-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-21 | 2010-04-22 | 2010-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-21 | 2014-04-22 | 2014-10-22 | $7700.00 | Window Closed / Lapsed |