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US6772359B2
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Clock control circuit for Rambus DRAM
Assignee: SK Hynix Inc
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Filing: 2000-11-30
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Granted: 2004-08-03
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Expires: 2020-11-30
Abstract
Abstract A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command. Our circuit includes: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with a device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with a device address value of a COLX packet is enabled, and when the command is a read or current control command; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting a control signal for maintaining the clock enable signal to the signal generating unit in the read or current control command; and an output signal control unit for outputting a control signal for controlling generation of the clock enable signal to the signal generating unit, when the command is not the read or current control command.
Inventors
- 👤 Jong Tae Kwak
- 👤 Dong Woo Shin
- 👤 Jong Sup Baek
- 👤 Choul Hee Koo
- 👤 Nak Kyu Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:32
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/325; G06F1/3275; G11; G11C; G11C7/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C7/22; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
230 words
A clock control circuit for a Rambus DRAM, comprising: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with an applied device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with an applied device address value of a COLX packet is enabled, and when the applied command is a read or a current control command, the command being applied with an SCP command packet on a Rambus DRAM module; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting to the signal generating unit a control signal for maintaining the clock enable signal generated from the signal generating unit in the read or the current control command; and an output signal control unit for outputting to the signal generating unit a control signal for controlling generation of the clock enable signal from the signal generating unit, when the command applied according to the enable signal from the input signal detecting unit is not the read or the current control command; wherein the COLC packet and the COLX packet include the read command or the current control command.
Claim 2
Dependent Claim
230 words
A clock control circuit for a Rambus DRAM, comprising: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with an applied device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with an applied device address value of a COLX packet is enabled, and when the applied command is a read or a current control command, the command being applied with an SCP command packet on a Rambus DRAM module; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting to the signal generating unit a control signal for maintaining the clock enable signal generated from the signal generating unit in the read or the current control command; and an output signal control unit for outputting to the signal generating unit a control signal for controlling generation of the clock enable signal from the signal generating unit, when the command applied according to the enable signal from the input signal detecting unit is not the read or the current control command; wherein the COLC packet and the COLX packet include the read command or the current control command.
Claim 3
Dependent Claim
116 words
The clock control circuit according to claim 1 , wherein the input signal detecting unit comprises: a first NAND gate for receiving a COP[1]signal(rqin2<1>signal) which is a bit implying the read or current control command in COP[3:0] which is an op_code of the COLC packet, and the first comparing signal; a second NAND gate for receiving a COP[1] signal(rqin3<3>signal) which is a bit implying the read or current control command in COP[3:0] which is an op_code of the COLX packet, and the second comparing signal; and an OR gate for receiving an inverted signal of the output signal from the first NAND gate and an inverted signal of the output signal from the second NAND gate.
Claim 4
Dependent Claim
168 words
The clock control circuit according to claim 1 , wherein the output signal control unit comprises: a first flip-flop for receiving the enable signal from the input signal detecting unit as an input signal, and a clock signal as a clock input; a second flip-flop for receiving an inverted signal of the output signal from the first flip-flop as an input signal, and the clock signal as a clock input; a third flip-flop for receiving the output signal from the second flip-flop as an input signal, and the clock signal as a clock input; an OR gate for receiving an inverted signal of the output signal from the third flip-flop and an inverted signal of a reset bar signal; and a fourth flip-flop for receiving the output signal from the input signal detecting unit as an enable signal, the output signal from the OR gate as a set signal, and a ground voltage as an input signal, and for outputting an output signal to the signal generating unit.
Claim 5
Dependent Claim
71 words
The clock control circuit according to claim 1 , wherein the signal generating unit comprises an OR gate for receiving an inverted signal of the first comparing signal, an inverted signal of the second comparing signal, an inverted signal of the output signal from the output signal control unit, and an inverted signal of the output signal from the output signal maintaining unit, and for generating the clock enable signal tclk_en.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-08-03 | 2008-02-02 | 2008-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-08-03 | 2012-02-02 | 2012-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-08-03 | 2016-02-02 | 2016-08-03 | $7700.00 | Window Closed / Lapsed |