Register controlled DLL for reducing current consumption

Claim 2

A semiconductor device having a register controlled delay locked loop (DLL) and an internal circuit synchronized with a DLL clock signal outputted from the register controlled DLL, the semiconductor device comprising: an enable signal generator generating an enable signal for the register controlled DLL to control a generation of the DLL clock signal in response to an activation or non-activation signal of the semiconductor device.

Claim 3

The semiconductor device as recited in claim 1 , further comprising: a control unit switching a signal transmission path to selectively transfer its input clock signal in response to the enable signal.

Claim 4

The semiconductor device as recited in claim 2 , wherein the control unit includes a NAND gate and an inverter.

Claim 5

The semiconductor device as recited in claim 2 , wherein the control unit includes a transfer transistor and an inverter.

Claim 6

The semiconductor device as recited in claim 1 , wherein the enable signal generator includes: a driving unit carrying out a pull-up or pull-down operation in response to the activation or non-activation signal of the semiconductor device; a reset unit resetting an output node of the driving unit; and a latch and buffering unit latching and buffering an output signal from the output node.

Claim 7

The semiconductor device as recited in claim 5 , wherein the activation signal is one of following: an activation command signal, a write enable signal, a read command signal, a column address strobe command signal, and a row address strobe command signal.

Claim 8

The semiconductor device as recited in claim 5 , wherein the non-activation signal is a precharge signal for precharging a bit line of a memory cell in the semiconductor device.

Claim 9

A register controlled delay locked loop (DLL) usable in a semiconductor device, the register controlled delay locked loop comprising: an internal clock generating unit generating an internal clock signal associated with an external clock signal, and generating a delayed clock signal and a reference clock signal; a first delay unit compensating for an amount of delay caused by a signal transmission path of the delayed clock signal; a phase comparator detecting a difference between the reference clock signal and the delayed clock signal and thereby generating a detection signal; a controller having a plurality of second delay units for controlling an amount of delay of the delayed clock signal in response to the detection signal from the phase comparator; a driver driving a DLL clock signal from the delayed clock signal having its delay amount controlled by the controller; an enable signal generator generating an enable signal in response to an activation or non-activation signal of the semiconductor device; and a clock control unit disposed between the internal clock generating unit and at least one of the second delay units, for selectively transferring the internal clock signal from the internal clock generating unit to the second delay unit in response to the enable signal.

Claim 10

A register controlled delay locked loop (DLL) usable in a semiconductor device, the register controlled delay locked loop comprising: an internal clock generating unit generating an internal clock signal associated with an external clock signal, and generating a delayed clock signal and a reference clock signal; a first delay unit compensating for an amount of delay caused by a signal transmission path of the delayed clock signal; a phase comparator detecting a difference between the reference clock signal and the delayed clock signal and thereby generating a detection signal; a controller having a plurality of second delay units for controlling an amount of delay of the delayed clock signal in response to the detection signal from the phase comparator; a driver driving a DLL clock signal from the delayed clock signal having its delay amount controlled by the controller; an enable signal generator generating an enable signal in response to an activation or non-activation signal of the semiconductor device; and a clock control unit disposed between the internal clock generating unit and at least one of the second delay units, for selectively transferring the internal clock signal from the internal clock generating unit to the second delay unit in response to the enable signal.

Claim 11

The register controlled delay locked loop as recited in claim 8 , wherein the enable signal generator includes: a driving unit carrying out a pull-up or pull-down operation in response to the activation or non-activation signal of the semiconductor device; a reset unit resetting an output node of the driving unit; and a latch and buffering unit latching and buffering an output from the output node.

Claim 12

The register controlled delay locked loop as recited in claim 8 , wherein the clock control unit includes a logic gate circuit passing the internal clock signal in response to an output signal from the enable signal generator.

Claim 13

The register controlled delay locked loop as recited in claim 8 , wherein the clock control unit includes a switching transfer gate to transfer the internal clock signal in response to both an output signal from the enable signal generator and an inverted signal of the output signal from the enable signal generator.