Patent US6738929B2 successfully refreshed from Google Patents.
US6738929B2
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Dynamically configurable debug port for concurrent support of debug functions from multiple data processing cores
Assignee: Texas Instruments Inc
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Filing: 2001-03-02
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Granted: 2004-05-18
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Expires: 2021-03-02
Abstract
Abstract An emulation controller ( 12 ) connected at a pin boundary of an integrated circuit ( 14 ) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2 , core 1 ) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin ( 39 ) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin ( 41 ) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.
Inventors
- 👤 Gary L. Swoboda
- 👤 Douglas E. Deao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:03
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31705; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/36; G06F11/362; G06F11/3632; G06F11/3636; G06F11/364; G06F11/3648; G06F11/3656; G06F9/00; G06F9/06; G06F9/44; G06F9/455; G06F11/30; G06F11/34; G06F11/3466; Y; Y02; Y02D; Y02D10/00; Y10; Y10S; Y10S370/00; Y10S370/914
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
234 words
An apparatus for providing to an emulation controller at a pin boundary of an integrated circuit concurrent access to concurrent debug signal activity of first and second data processing cores embedded within the integrated circuit, comprising: a first signal path from the first data processing core to a first pin of the integrated circuit for carrying a selected debug signal of the first data processing core to the first pin; a second signal path from the second data processing core to said first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to said first pin; a third signal path from the second data processing core to a second pin of the integrated circuit for carrying said selected debug signal of the second data processing core to said second pin; a first multiplexer having an output coupled to said first pin and having first and second inputs respectively coupled to said first and second data processing cores, wherein said first multiplexer defines a portion of said first signal path and a portion of said second signal path; a second multiplexer having an output coupled to said second pin and having an input coupled to said second core, wherein said second multiplexer defines a portion of said third signal path; and a register coupled to a control input of one of said multiplexers for controlling operation thereof.
Claim 2
Independent Claim
234 words
An apparatus for providing to an emulation controller at a pin boundary of an integrated circuit concurrent access to concurrent debug signal activity of first and second data processing cores embedded within the integrated circuit, comprising: a first signal path from the first data processing core to a first pin of the integrated circuit for carrying a selected debug signal of the first data processing core to the first pin; a second signal path from the second data processing core to said first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to said first pin; a third signal path from the second data processing core to a second pin of the integrated circuit for carrying said selected debug signal of the second data processing core to said second pin; a first multiplexer having an output coupled to said first pin and having first and second inputs respectively coupled to said first and second data processing cores, wherein said first multiplexer defines a portion of said first signal path and a portion of said second signal path; a second multiplexer having an output coupled to said second pin and having an input coupled to said second core, wherein said second multiplexer defines a portion of said third signal path; and a register coupled to a control input of one of said multiplexers for controlling operation thereof.
Claim 3
Dependent Claim
15 words
The apparatus of claim 1 , wherein said register is provided within said integrated circuit.
Claim 4
Dependent Claim
41 words
The apparatus of claim 1 , including a further signal path from the first data processing core to a further pin of the integrated circuit for carrying the selected debug signal of the first data processing core to the further pin.
Claim 5
Dependent Claim
21 words
The apparatus of claim 1 , wherein said selected debug signal of the first data processing core is a trace signal.
Claim 6
Dependent Claim
21 words
The apparatus of claim 4 , wherein the selected debug signal of the second data processing core is a trace signal.
Claim 7
Dependent Claim
21 words
The apparatus of claim 4 , wherein the selected debug signal of the second data processing core is a trigger signal.
Claim 8
Dependent Claim
217 words
A data processing integrated circuit, comprising: first and second embedded data processing cores for performing data processing operations; a first signal path from the first data processing core to a first pin of the integrated circuit for carrying a selected debug signal of the first data processing core to the first pin; a second signal path from the second data processing core to said first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to said first pin; and a third signal path from the second data processing core to a second pin of the integrated circuit for carrying said selected debug signal of the second data processing core to said second pin; a first multiplexer having an output coupled to said first pin and having first and second inputs respectively coupled to said first and second data processing cores, wherein said first multiplexer defines a portion of said first signal path and a portion of said second signal path; a second multiplexer having an output coupled to said second pin and having an input coupled to said second core, wherein said second multiplexer defines a portion of said third signal path; and a register coupled to a control input of one of said multiplexers for controlling operation thereof.
Claim 9
Dependent Claim
217 words
A data processing integrated circuit, comprising: first and second embedded data processing cores for performing data processing operations; a first signal path from the first data processing core to a first pin of the integrated circuit for carrying a selected debug signal of the first data processing core to the first pin; a second signal path from the second data processing core to said first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to said first pin; and a third signal path from the second data processing core to a second pin of the integrated circuit for carrying said selected debug signal of the second data processing core to said second pin; a first multiplexer having an output coupled to said first pin and having first and second inputs respectively coupled to said first and second data processing cores, wherein said first multiplexer defines a portion of said first signal path and a portion of said second signal path; a second multiplexer having an output coupled to said second pin and having an input coupled to said second core, wherein said second multiplexer defines a portion of said third signal path; and a register coupled to a control input of one of said multiplexers for controlling operation thereof.
Claim 10
Dependent Claim
126 words
A data processing integrated circuit, comprising: a plurality of embedded data processing cores for performing data processing operations, each embedded data processing core having at least one debug output signal line having a debug signal thereon; a plurality of debug output pins; a plurality of multiplexers, each multiplexer having a plurality of inputs connected to corresponding debug output signal lines, a control input and an output connected to a corresponding one of said debug output pins, each multiplexer selectively coupling one of said plurality of inputs to said output dependent upon said control input; and a register loadable from external of said data processing integrated circuit and connected to said control inputs of said multiplexers, said register storing data controlling said selectively coupling of said multiplexers.
Claim 11
Dependent Claim
126 words
A data processing integrated circuit, comprising: a plurality of embedded data processing cores for performing data processing operations, each embedded data processing core having at least one debug output signal line having a debug signal thereon; a plurality of debug output pins; a plurality of multiplexers, each multiplexer having a plurality of inputs connected to corresponding debug output signal lines, a control input and an output connected to a corresponding one of said debug output pins, each multiplexer selectively coupling one of said plurality of inputs to said output dependent upon said control input; and a register loadable from external of said data processing integrated circuit and connected to said control inputs of said multiplexers, said register storing data controlling said selectively coupling of said multiplexers.
Claim 12
Dependent Claim
74 words
The data processing integrated circuit of claim 8 , further comprising: a plurality of tri-state buffers, each tri-state buffer having an input connected to said output of a corresponding one of said multiplexers, an output connected to a corresponding one of said debug output pins and a control input connected to said register; and wherein said register stores data controlling whether each of said plurality of tri-state buffers produces a tri-state high Z output.
Claim 13
Dependent Claim
35 words
The data processing integrated circuit of claim 8 , wherein: at least one of said plurality of multiplexers has an input connected to said debug output signal lines of at least two data processing cores.
Claim 14
Dependent Claim
54 words
The data processing integrated circuit of claim 8 , wherein: at least one of said plurality of multiplexers has a first input connected to a first debug output signal line of a predetermined data processing core and a second input connected to a second debug output signal line of said predetermined data processing core.
Claim 15
Dependent Claim
53 words
The data processing integrated circuit of claim 8 , wherein: a first multiplexer has a first input connected to a first debug output signal line of a predetermined data processing core; and a second multiplexer has a first input connected to said first debug output signal line of said predetermined data processing core.
Claim 16
Dependent Claim
38 words
The data processing integrated circuit of claim 8 , wherein: said register is loadable from external of said data processing integrated circuit during operation of said data processing integrated circuit thereby changing said selectively coupling of said multiplexers.
References Cited (Backward Citations)
US5828824A
Cited
US20020147939A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-05-18 | 2007-11-17 | 2008-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-05-18 | 2011-11-17 | 2012-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-05-18 | 2015-11-17 | 2016-05-18 | $7700.00 | Window Closed / Lapsed |