Patent US6731148B2 successfully refreshed from Google Patents.
US6731148B2
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Apparatus and method for generating clock signals
Assignee: Rambus Inc
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Filing: 2002-05-29
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Granted: 2004-05-04
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Expires: 2022-05-29
Abstract
Abstract A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period. A second delay element is coupled to receive the first clock signal from the delay-locked loop circuit. The second delay element also outputs a second clock signal that is delayed relative to the first clock signal by the first time period. The delay-locked loop circuit may include a phase detector to identify phase differences between the first clock signal and the reference clock signal. A third delay element may be coupled between the delay-locked loop circuit and the second delay element.
Inventors
- 👤 Benedict C. Lau
- 👤 Stefanos Sidiropoulos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:20
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
97 words
An apparatus comprising: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; and a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period wherein the second delay element is outside the feedback path.
Claim 2
Independent Claim
97 words
An apparatus comprising: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; and a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period wherein the second delay element is outside the feedback path.
Claim 3
Dependent Claim
31 words
An apparatus as recited in claim 1 wherein the delay-locked loop circuit further includes a phase detector to identify phase differences between the first clock signal and the reference clock signal.
Claim 4
Dependent Claim
16 words
An apparatus as recited in claim 2 wherein the phase detector is a zero phase detector.
Claim 5
Dependent Claim
28 words
An apparatus as recited in claim 2 wherein the phase detector is an integration sampler to integrate the first clock signal with respect to the reference clock signal.
Claim 6
Dependent Claim
28 words
An apparatus as recited in claim 1 wherein the delay-locked loop circuit further includes a 180 degree phase shifter to adjust the phase of the first clock signal.
Claim 7
Dependent Claim
21 words
An apparatus as recited in claim 1 wherein the first clock signal indicates when to transmit data onto a data bus.
Claim 8
Dependent Claim
21 words
An apparatus as recited in claim 1 wherein the second clock signal indicates when to receive data from a data bus.
Claim 9
Dependent Claim
19 words
An apparatus as recited in claim 1 wherein the second delay element is separate from the delay-locked loop circuit.
Claim 10
Independent Claim
91 words
A method comprising: generating a first clock signal using a delay-locked loop circuit; advancing the first clock signal relative to a reference clock signal by a first time period using a first delay element coupled in the feedback path of the delay-locked loop circuit; and generating a second clock signal that is delayed relative to the first clock signal by the first time period using a second delay element coupled to receive the first clock signal, wherein the second delay element is outside the feedback path of the delay-locked loop circuit.
Claim 11
Independent Claim
91 words
A method comprising: generating a first clock signal using a delay-locked loop circuit; advancing the first clock signal relative to a reference clock signal by a first time period using a first delay element coupled in the feedback path of the delay-locked loop circuit; and generating a second clock signal that is delayed relative to the first clock signal by the first time period using a second delay element coupled to receive the first clock signal, wherein the second delay element is outside the feedback path of the delay-locked loop circuit.
Claim 12
Dependent Claim
24 words
A method as recited in claim 9 further including transmitting data onto a data bus based on the state of the first clock signal.
Claim 13
Dependent Claim
24 words
A method as recited in claim 9 further including receiving data from a data bus based on the state of the first clock signal.
Claim 14
Dependent Claim
23 words
A method as recited in claim 9 further including identifying the phase differences between the first clock signal and the reference clock signal.
Claim 15
Independent Claim
132 words
A method, comprising: generating a first clock signal using a delay-locked loop circuit; advancing the first clock signal relative to a reference clock signal by a first time period using a first delay element coupled in the feedback path of the delay-locked loop circuit; generating a first clock signal using a delay-locked loop circuit; advancing the first clock signal relative to a reference clock signal by a first time period using a first delay element coupled in the feedback path of the delay-locked loop circuit; and generating a second clock signal that is delayed relative to the first clock signal by the first time period using a second delay element coupled to receive the first clock signal, wherein the second delay element is outside the feedback path of the delay-locked loop circuit.
Claim 16
Independent Claim
132 words
A method, comprising: generating a first clock signal using a delay-locked loop circuit; advancing the first clock signal relative to a reference clock signal by a first time period using a first delay element coupled in the feedback path of the delay-locked loop circuit; generating a first clock signal using a delay-locked loop circuit; advancing the first clock signal relative to a reference clock signal by a first time period using a first delay element coupled in the feedback path of the delay-locked loop circuit; and generating a second clock signal that is delayed relative to the first clock signal by the first time period using a second delay element coupled to receive the first clock signal, wherein the second delay element is outside the feedback path of the delay-locked loop circuit.
Claim 17
Dependent Claim
124 words
A memory system comprising: a memory storage device; a data bus coupled to the memory storage device; and a memory controller coupled to the data bus, the memory controller including: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; and a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period, wherein the second delay element is outside the feedback path.
Claim 18
Dependent Claim
124 words
A memory system comprising: a memory storage device; a data bus coupled to the memory storage device; and a memory controller coupled to the data bus, the memory controller including: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; and a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period, wherein the second delay element is outside the feedback path.
Claim 19
Dependent Claim
30 words
A memory system as recited in claim 14 wherein the delay-locked loop circuit includes a phase detector to identify phase differences between the first clock signal and the reference clock.
Claim 20
Dependent Claim
17 words
A memory system as recited in claim 15 wherein the phase detector is a zero phase detector.
Claim 21
Dependent Claim
22 words
A memory system as recited in claim 14 wherein the first clock signal indicates when to transmit data onto the data bus.
Claim 22
Dependent Claim
22 words
A memory system as recited in claim 14 wherein the second clock signal indicates when to receive data from the data bus.
Claim 23
Dependent Claim
20 words
A memory system as recited in claim 14 wherein the second delay element is separate from the delay-locked loop circuit.
Claim 24
Dependent Claim
158 words
A memory system comprising: a memory storage device; a data bus coupled to the memory storage device; a memory controller coupled to the data bus, the memory controller including: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including: a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; a phase detector to identify phase differences between the first clock signal and the reference clock, wherein the phase detector is an integration sampler to integrate the first clock signal against the reference clock signal; and a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period, wherein the second delay element is outside the feedback path.
Claim 25
Dependent Claim
158 words
A memory system comprising: a memory storage device; a data bus coupled to the memory storage device; a memory controller coupled to the data bus, the memory controller including: a delay-locked loop circuit to generate a first clock signal, the delay-locked loop circuit including: a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period; a phase detector to identify phase differences between the first clock signal and the reference clock, wherein the phase detector is an integration sampler to integrate the first clock signal against the reference clock signal; and a second delay element coupled to receive the first clock signal from the delay-locked loop circuit and to output a second clock signal that is delayed relative to the first clock signal by the first time period, wherein the second delay element is outside the feedback path.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2007-05-04 | 2007-11-03 | 2008-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-05-04 | 2011-11-03 | 2012-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-05-04 | 2015-11-03 | 2016-05-04 | $7700.00 | Window Closed / Lapsed |