US6727592B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Copper interconnect with improved barrier layer
Assignee: Advanced Micro Devices Inc
•
Filing: 2002-02-22
•
Granted: 2004-04-27
•
Expires: 2022-02-22
Abstract
Abstract A Cu interconnect, e.g.; a dual damascene structure, is formed with improved electromigration resistance and increased via chain yield by depositing a barrier layer in an opening by CVD, depositing a flash layer of α-Ta by PVD, at a thickness less than 30 Å, on the bottom of the barrier layer, depositing a seedlayer and then filling the opening with Cu. Embodiments include depositing a thin α-Ta layer, as at a thickness less than 10 Å, and/or as discontinuous regions of clusters of atoms on sides of the opening.
Inventors
- 👤 Christy Mei-Chu Woo
- 👤 John E. Sanchez
- 👤 Darrell M. Erb
- 👤 Amit P. Marathe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:24
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10W20/035; H10W20/041; H10W20/042; H10W20/40; H10W20/41; H10W20/425
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
100 words
A semiconductor device comprising: an opening formed in a dielectric layer; a barrier layer lining the opening, the barrier layer comprising a bottom portion and side portions; a layer of tantalum (Ta), deposited by physical vapor deposition and having a thickness less than 30 Å, on the bottom portion of the barrier layer; discontinuous regions of clusters of Ta atoms on the side portions of the barrier layer; a seedlayer on the layer of Ta and over the side portions of the barrier layer and the clusters of Ta atoms; and copper (Cu) or a Cu alloy filling the opening.
Claim 2
Dependent Claim
100 words
A semiconductor device comprising: an opening formed in a dielectric layer; a barrier layer lining the opening, the barrier layer comprising a bottom portion and side portions; a layer of tantalum (Ta), deposited by physical vapor deposition and having a thickness less than 30 Å, on the bottom portion of the barrier layer; discontinuous regions of clusters of Ta atoms on the side portions of the barrier layer; a seedlayer on the layer of Ta and over the side portions of the barrier layer and the clusters of Ta atoms; and copper (Cu) or a Cu alloy filling the opening.
Claim 3
Dependent Claim
50 words
The semiconductor device according to claim 1 , wherein the barrier layer comprises a material selected from the group consisting of tantalum nitride, titanium silicon nitride, tungsten nitride, titanium, titanium-tungsten, tungsten, titanium-titanium nitride, tungsten silicon nitride, tantalum silicon nitride silicon nitride and titanium nitride with a layer of silicon thereon.
Claim 4
Dependent Claim
16 words
The semiconductor device according to claim 1 , wherein the layer of Ta comprises alpha (2)-Ta.
Claim 5
Dependent Claim
37 words
The semiconductor device according to claim 1 , wherein the opening is a dual damascene opening and the filled opening comprises an upper Cu or Cu alloy line connected to a lower Cu or Cu alloy via.
Claim 6
Dependent Claim
25 words
The semiconductor device according to claim 1 , wherein the layer of Ta layer has a thickness of about 5 Å to about 30 Å.
Claim 7
Dependent Claim
24 words
The semiconductor device according to claim 5 , wherein the layer of Ta has a thickness of about 8 Å to about 24 Å.
Claim 8
Dependent Claim
101 words
A semiconductor device comprising: an opening formed in a dielectric layer; a barrier layer lining the opening, the barrier layer comprising a bottom portion and side portions; a first layer of tantalum (Ta) deposited by physical vapor deposition and having a thickness less than 30 Å, on the bottom portion of the barrier layer; a discontinuous second layer of Ta, having a thickness less than 10 Å, on the side portions of the barrier layer; a seedlayer on the first layer of Ta and in direct contact with the barrier layer; and copper (Cu) or a Cu alloy filling the opening.
Claim 9
Dependent Claim
101 words
A semiconductor device comprising: an opening formed in a dielectric layer; a barrier layer lining the opening, the barrier layer comprising a bottom portion and side portions; a first layer of tantalum (Ta) deposited by physical vapor deposition and having a thickness less than 30 Å, on the bottom portion of the barrier layer; a discontinuous second layer of Ta, having a thickness less than 10 Å, on the side portions of the barrier layer; a seedlayer on the first layer of Ta and in direct contact with the barrier layer; and copper (Cu) or a Cu alloy filling the opening.
Claim 10
Dependent Claim
31 words
The semiconductor device according to claim 7 , wherein the discontinuous second layer of Ta on the side portions of the barrier layer has a thickness less than about 3 Å.
Claim 11
Independent Claim
114 words
A method of manufacturing a semiconductor device, the method comprising: forming an opening in a dielectric layer; depositing a barrier layer by chemical vapor deposition or atomic layer deposition lining the opening, the barrier layer comprising a bottom portion and side portions; depositing a layer of tantalum (Ta) by physical vapor deposition, at a thickness less than 30 Å, on the bottom portion of the barrier layer; depositing discontinuous regions of clusters of Ta atoms by physical vapor deposition on side portions of the barrier layer; depositing a seedlayer on the layer of Ta and over the side portions of the barrier layer; and filling the opening with copper (Cu) or a Cu alloy.
Claim 12
Independent Claim
114 words
A method of manufacturing a semiconductor device, the method comprising: forming an opening in a dielectric layer; depositing a barrier layer by chemical vapor deposition or atomic layer deposition lining the opening, the barrier layer comprising a bottom portion and side portions; depositing a layer of tantalum (Ta) by physical vapor deposition, at a thickness less than 30 Å, on the bottom portion of the barrier layer; depositing discontinuous regions of clusters of Ta atoms by physical vapor deposition on side portions of the barrier layer; depositing a seedlayer on the layer of Ta and over the side portions of the barrier layer; and filling the opening with copper (Cu) or a Cu alloy.
Claim 13
Dependent Claim
44 words
The method according to claim 9 , comprising depositing the barrier layer of a material selected from a group consisting of tantalum nitride, titanium nitride, titanium, titanium-tungsten, tungsten, tungsten nitride, titanium-titanium nitride, titanium silicon nitride, tungsten silicon nitride, tantalum silicon nitride and silicon nitride.
Claim 14
Dependent Claim
24 words
The method according to claim 9 , comprising a depositing a layer of alpha (2)-Ta as the layer of Ta by physical vapor deposition.
Claim 15
Dependent Claim
42 words
The method according to claim 9 , comprising: forming the opening as a dual damascene opening; and filling the opening with the Cu or Cu alloy to form a Cu or Cu alloy line connected to a Cu or Cu alloy via.
Claim 16
Dependent Claim
24 words
The method according to claim 9 , comprising depositing the layer of Ta at a thickness of about 5 Å to about 30 Å.
Claim 17
Dependent Claim
24 words
The method according to claim 13 , comprising depositing the layer of Ta at a thickness of about 8 Å to about 24 Å.
Claim 18
Independent Claim
119 words
A method of manufacturing a semiconductor device, the method comprising: forming an opening in a dielectric layer: depositing a barrier layer by chemical vapor deposition or atomic layer deposition lining the opening, the barrier layer comprising a bottom portion and side portions; depositing a first layer of tantalum (Ta) by physical vapor deposition at a thickness less than 30 Å, on the bottom portion of the barrier layer; depositing a discontinuous second layer of Ta on the side portions of the barrier layer at a thickness less than about 10 Å; depositing a seedlayer on the first layer of Ta and in direct contact with the barrier layer; and filling the opening with copper (Cu) or a Cu alloy.
Claim 19
Independent Claim
119 words
A method of manufacturing a semiconductor device, the method comprising: forming an opening in a dielectric layer: depositing a barrier layer by chemical vapor deposition or atomic layer deposition lining the opening, the barrier layer comprising a bottom portion and side portions; depositing a first layer of tantalum (Ta) by physical vapor deposition at a thickness less than 30 Å, on the bottom portion of the barrier layer; depositing a discontinuous second layer of Ta on the side portions of the barrier layer at a thickness less than about 10 Å; depositing a seedlayer on the first layer of Ta and in direct contact with the barrier layer; and filling the opening with copper (Cu) or a Cu alloy.
Claim 20
Dependent Claim
30 words
The method according to claim 15 , comprising depositing the discontinuous second layer of Ta on side portions of the barrier layer at a thickness less than about 3 Å.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-04-27 | 2007-10-27 | 2008-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-04-27 | 2011-10-27 | 2012-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-04-27 | 2015-10-27 | 2016-04-27 | $7700.00 | Window Closed / Lapsed |