Patent US6718522B1 successfully refreshed from Google Patents.
US6718522B1
Expired / Lapsed
US
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Electrical rules checker system and method using tri-state logic for electrical rule checks
Assignee: Samsung Electronics Co Ltd
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Filing: 2000-08-15
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Granted: 2004-04-06
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Expires: 2020-08-15
Abstract
Abstract An electrical rules checker system and method are provided to identify tri-state logic from a netlist. In accordance with one aspect of the invention, a method identifies tri-state logic from a netlist by selecting a circuit configuration to be identified, and then identifying any of the circuit configurations at the node, and identifyng any probable circuit configurations at the node. In accordance with another aspect of the invention, a system is provided for identifying tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist.
Inventors
- 👤 John G McBride
- 👤 Jan Kok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:55
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
72 words
A method for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising the steps of: selecting a circuit configuration to be identified, wherein the circuit configuration defines a tri-state logic configuration; identifying known circuit configurations at the node; identifying probable circuit configurations at the node; and determining whether the selected circuit configuration is an identified known or identified probably circuit configuration.
Claim 2
Independent Claim
72 words
A method for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising the steps of: selecting a circuit configuration to be identified, wherein the circuit configuration defines a tri-state logic configuration; identifying known circuit configurations at the node; identifying probable circuit configurations at the node; and determining whether the selected circuit configuration is an identified known or identified probably circuit configuration.
Claim 3
Dependent Claim
24 words
The method as defined in claim 1 , wherein the step of selecting a circuit configuration includes identifying a complementary pass FET circuit configuration.
Claim 4
Dependent Claim
25 words
The method as defined in claim 1 , wherein the step of selecting a circuit configuration includes identifying a special complementary pass FET circuit configuration.
Claim 5
Dependent Claim
23 words
The method as defined in claim 1 , wherein the step of selecting a circuit configuration includes identifying a gate output circuit configuration.
Claim 6
Dependent Claim
23 words
The method as defined in claim 1 , wherein the step of selecting a circuit configuration includes identifying a RAM cell circuit configuration.
Claim 7
Dependent Claim
23 words
The method as defined in claim 1 , wherein the step of selecting a circuit configuration includes identifying a feedback FET circuit configuration.
Claim 8
Dependent Claim
24 words
The method as defined in claim 1 , wherein the step of selecting a circuit configuration includes identifying a single pass FET circuit configuration.
Claim 9
Independent Claim
77 words
A system for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting a circuit configuration to be identified, wherein the circuit configuration defines a tri-state logic configuration; means for identifying known circuit configurations at the node; means for identifying probable circuit configurations at the node; and means for determining whether the selected circuit configuration is an identified known or identified probably circuit configuration.
Claim 10
Independent Claim
77 words
A system for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting a circuit configuration to be identified, wherein the circuit configuration defines a tri-state logic configuration; means for identifying known circuit configurations at the node; means for identifying probable circuit configurations at the node; and means for determining whether the selected circuit configuration is an identified known or identified probably circuit configuration.
Claim 11
Dependent Claim
38 words
The system of claim 8 , further comprising: means for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting complementary pass FET circuit configurations.
Claim 12
Dependent Claim
39 words
The system of claim 8 , further comprising: means for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting special complementary pass FET circuit configurations.
Claim 13
Dependent Claim
37 words
The system of claim 8 , further comprising: means for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting gate output circuit configurations.
Claim 14
Dependent Claim
37 words
The system of claim 8 , further comprising: means for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting RAM cell circuit configurations.
Claim 15
Dependent Claim
37 words
The system of claim 8 , further comprising: means for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting feedback FET circuit configurations.
Claim 16
Dependent Claim
38 words
The system of claim 8 , further comprising: means for identifying tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting single pass FET circuit configurations.
Claim 17
Dependent Claim
113 words
A computer readable storage medium containing program code for identifying tri-state logic connected to a selected node of an integrated circuit and marking each such identified FET by setting a flag in a data structure associated with the FET comprising: a first code segment configured to select a circuit configuration to be identified, wherein the circuit configuration defines a tri-state logic configuration; a second code segment configured to identify known circuit configurations in a netlist; a third code segment configured to identify probable circuit configurations at the node in a netlist; and a fourth code segment configured to determine whether the selected circuit configuration is an identified known or identified probably circuit configuration.
Claim 18
Dependent Claim
113 words
A computer readable storage medium containing program code for identifying tri-state logic connected to a selected node of an integrated circuit and marking each such identified FET by setting a flag in a data structure associated with the FET comprising: a first code segment configured to select a circuit configuration to be identified, wherein the circuit configuration defines a tri-state logic configuration; a second code segment configured to identify known circuit configurations in a netlist; a third code segment configured to identify probable circuit configurations at the node in a netlist; and a fourth code segment configured to determine whether the selected circuit configuration is an identified known or identified probably circuit configuration.
Claim 19
Dependent Claim
36 words
The program code of claim 15 , wherein said second code segment is further configured to set a complementary pass FET flag in the data structure for the identified elements that comprise a complementary pass FET.
Claim 20
Dependent Claim
37 words
The program code of claim 15 , wherein said second code segment is further configured to set a special complementary pass FET flag in the data structure for identified elements that comprise a special complementary pass FET.
Claim 21
Dependent Claim
34 words
The program code of claim 15 , wherein said second code segment is further configured to set a gate output flag in the data structure for the identified elements that comprise a gate output.
Claim 22
Dependent Claim
34 words
The program code of claim 15 , wherein said second code segment is further configured to set a RAM cell flag in the data structure for the identified elements that comprise a RAM cell.
Claim 23
Dependent Claim
34 words
The program code of claim 15 , wherein said second code segment is further configured to set a feedback FET flag in the data structure for the identified elements that comprise a feedback FET.
Claim 24
Dependent Claim
35 words
The program code of claim 15 , wherein said second code segment is further configured to set a single pass FET flag in the data structure for identified elements that comprise a single pass FET.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-04-06 | 2007-10-06 | 2008-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-04-06 | 2011-10-06 | 2012-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-04-06 | 2015-10-06 | 2016-04-06 | $7700.00 | Window Closed / Lapsed |