Generator for the production of clock signals

Claim 2

A signal generator comprising: a frequency divider for providing a low-frequency signal that is based upon a high-frequency output signal, and for providing a driving signal representative of a frequency of the high-frequency output signal; a comparator connected to said frequency divider for comparing a phase of the low-frequency signal with a phase of a reference signal, and for providing at least one control signal having a duration based upon the comparison; oscillator driving means connected to said frequency divider for receiving the driving signal, and for modulating a value of a coefficient of proportionality based upon a difference between the frequency of the high-frequency output signal and a desired frequency; an oscillator connected to said comparator and to said oscillator driving means for providing the high-frequency output signal having a frequency based upon the duration of the at least one control signal multiplied by the coefficient of proportionality; and a reset circuit connected to said frequency divider and to said phase comparator for providing a reset signal at each leading edge of the reference signal for synchronizing the low-frequency signal with the reference signal.

Claim 3

A signal generator according to claim 1 , wherein said frequency divider has a reset input for receiving the reset signal.

Claim 4

A signal generator according to claim 1 , wherein said comparator has an input for receiving the reset signal for deactivating the at least one control signal at each leading edge of the reference signal.

Claim 5

A signal generator according to claim 1 , wherein said reset circuit comprises: a first flip-flop circuit comprising a data input for receiving the reference signal, and an input for receiving the high-frequency output signal; and a first logic gate having a first input connected to the data input of said first flip-flop circuit, a second input connected to a data output of said first flip-flop circuit, and an output for providing the reset signal.

Claim 6

A signal generator according to claim 1 , wherein said frequency divider comprises: a counter for counting pulses of the high-frequency output signal and for providing a stop signal when a number of counted pulses reaches a first number; a second flip-flop circuit having an input for receiving the stop signal, a data input, and an output connected to the data input and for providing the low-frequency signal; an inverter having an input for receiving the stop signal; and a second logic gate having a first input connected to an output of said inverter for receiving the stop signal, a second input for receiving the reset signal, and an output connected to said counter for providing a setting signal thereto.

Claim 7

A signal generator according to claim 5 , wherein the setting signal is active when at least one of the stop and reset signals are active.

Claim 8

A signal generator according to claim 5 , wherein said second flip-flop circuit has an input for receiving the reset signal.

Claim 9

A signal generator according to claim 5 , wherein said frequency divider further comprises a third flip-flop circuit connected between said counter and said oscillator driving means for providing a binary number equal to the number of counted pulses in the high-frequency output signal during a half-period of the reference signal and representing the frequency of the high-frequency output signal.

Claim 10

A signal generator according to claim 8 , wherein said oscillator driving means increases the value of the coefficient of proportionality if the binary number is significantly different from a desired number, and reduces the value of the coefficient of proportionality if the binary number is close to the desired number.

Claim 11

A signal generator according to claim 8 , wherein said oscillator driving means linearly modulates the coefficient of proportionality as a function of a difference between the binary number and a desired number.

Claim 12

A signal generator according to claim 8 , wherein said oscillator driving means modulates the coefficient of proportionality so that the coefficient of proportionality takes a first value when an absolute value of a difference between the binary number is less than a threshold, otherwise the coefficient of proportionality takes a second value.

Claim 13

A signal generator according to claim 1 , wherein said frequency divider, said comparator, said oscillator driving means, said oscillator and said reset circuit form an integrated circuit.

Claim 14

A signal generator comprising: a frequency divider for providing a low-frequency signal based upon a high-frequency output signal, and for providing a driving signal representative of a frequency of the high-frequency output signal; a comparator connected to said frequency divider for comparing a phase of the low-frequency signal with a phase of a reference signal, and for providing at least one control signal having a duration based upon the comparison; an oscillator driving circuit connected to said frequency divider for receiving the driving signal, and for modulating a value of a coefficient of proportionality based upon a difference between the frequency of the high-frequency output signal and a desired frequency; an oscillator connected to said comparator and to said oscillator driving circuit for providing the high-frequency output signal having a frequency based upon the duration of the at least one control signal multiplied by the coefficient of proportionality; and a reset circuit connected to said frequency divider and to said phase comparator for providing a reset signal based upon the reference signal for synchronizing the low-frequency signal with the reference signal.

Claim 15

A signal generator comprising: a frequency divider for providing a low-frequency signal based upon a high-frequency output signal, and for providing a driving signal representative of a frequency of the high-frequency output signal; a comparator connected to said frequency divider for comparing a phase of the low-frequency signal with a phase of a reference signal, and for providing at least one control signal having a duration based upon the comparison; an oscillator driving circuit connected to said frequency divider for receiving the driving signal, and for modulating a value of a coefficient of proportionality based upon a difference between the frequency of the high-frequency output signal and a desired frequency; an oscillator connected to said comparator and to said oscillator driving circuit for providing the high-frequency output signal having a frequency based upon the duration of the at least one control signal multiplied by the coefficient of proportionality; and a reset circuit connected to said frequency divider and to said phase comparator for providing a reset signal based upon the reference signal for synchronizing the low-frequency signal with the reference signal.

Claim 16

A signal generator according to claim 13 , wherein said frequency divider has a reset input for receiving the reset signal.

Claim 17

A signal generator according to claim 13 , wherein said reset circuit provides the reset signal at each leading edge of the reference signal; and wherein said comparator has an input for receiving the reset signal for deactivating the at least one control signal at each leading edge of the reference signal.

Claim 18

A signal generator according to claim 13 , wherein said reset circuit comprises: a first flip-flop circuit comprising a data input for receiving the reference signal, and an input for receiving the high-frequency output signal; and a first logic gate having a first input connected to the data input of said first flip-flop circuit, a second input connected to a data output of said first flip-flop circuit, and an output for providing the reset signal.

Claim 19

A signal generator according to claim 13 , wherein said frequency divider comprises: a counter for counting pulses of the high-frequency output signal and for providing a stop signal when a number of counted pulses reaches a first number; a second flip-flop circuit having an input for receiving the stop signal, a data input, and an output connected to the data input and for providing the low-frequency signal; an inverter having an input for receiving the stop signal; and a second logic gate having a first input connected to an output of said inverter for receiving the stop signal, a second input for receiving the reset signal, and an output connected to said counter for providing a setting signal thereto.

Claim 20

A signal generator according to claim 17 , wherein said second flip-flop circuit has an input for receiving the reset signal.

Claim 21

A signal generator according to claim 17 , wherein said frequency divider further comprises a third flip-flop circuit connected between said counter and said oscillator driving circuit for providing a binary number equal to the number of counted pulses in the high-frequency output signal during a half-period of the reference signal and representing the frequency of the high-frequency output signal.

Claim 22

A signal generator according to claim 19 , wherein said oscillator driving circuit increases a value of the coefficient of proportionality if the binary number is significantly different from a desired number, and reduces the value of the coefficient of proportionality if the binary number is close to the desired number.

Claim 23

A signal generator according to claim 19 , wherein said oscillator driving circuit linearly modulates the coefficient of proportionality as a function of a difference between the binary number and a desired number.

Claim 24

A signal generator according to claim 19 , wherein said oscillator driving circuit modulates the coefficient of proportionality so that the coefficient of proportionality takes a first value when an absolute value of a difference between the binary number is less than a threshold, otherwise the coefficient of proportionality takes a second value.

Claim 25

A clock signal generator comprising: a frequency divider for providing a low-frequency signal based upon a high-frequency clock signal, and for providing a driving signal representative of a frequency of the high-frequency output signal; a comparator connected to said frequency divider for comparing a phase of the low-frequency signal with a phase of a reference signal, and for providing at least one control-signal having a duration based upon the comparison; an oscillator driving circuit connected to said frequency divider for receiving the driving signal, and for modulating a value of a coefficient of proportionality based upon a difference between the frequency of the high-frequency output signal and a desired frequency; an oscillator connected to said comparator and to said oscillator driving circuit for providing the high-frequency clock signal having a frequency based upon the duration of the at least one control signal multiplied by a the coefficient of proportionality; and a reset circuit connected to said frequency divider and to said phase comparator for providing a reset signal at each leading edge of the reference signal for synchronizing the low-frequency signal with the reference signal, said reset circuit comprising a first flip-flop circuit comprising a data input for receiving the reference signal, and an input for receiving the high-frequency clock signal, and a first logic gate having a first input connected to the data input of said first flip-flop circuit, a second input connected to a data output of said first flip-flop circuit, and an output for providing the reset signal.

Claim 26

A clock signal generator comprising: a frequency divider for providing a low-frequency signal based upon a high-frequency clock signal, and for providing a driving signal representative of a frequency of the high-frequency output signal; a comparator connected to said frequency divider for comparing a phase of the low-frequency signal with a phase of a reference signal, and for providing at least one control-signal having a duration based upon the comparison; an oscillator driving circuit connected to said frequency divider for receiving the driving signal, and for modulating a value of a coefficient of proportionality based upon a difference between the frequency of the high-frequency output signal and a desired frequency; an oscillator connected to said comparator and to said oscillator driving circuit for providing the high-frequency clock signal having a frequency based upon the duration of the at least one control signal multiplied by a the coefficient of proportionality; and a reset circuit connected to said frequency divider and to said phase comparator for providing a reset signal at each leading edge of the reference signal for synchronizing the low-frequency signal with the reference signal, said reset circuit comprising a first flip-flop circuit comprising a data input for receiving the reference signal, and an input for receiving the high-frequency clock signal, and a first logic gate having a first input connected to the data input of said first flip-flop circuit, a second input connected to a data output of said first flip-flop circuit, and an output for providing the reset signal.

Claim 27

A clock signal generator according to claim 23 , wherein said comparator has an input for receiving the reset signal for deactivating the at least one control signal at each leading edge of the reference signal.

Claim 28

A clock signal generator according to claim 23 , wherein said frequency divider comprises: a counter for counting pulses of the high-frequency clock signal and for providing a stop signal when a number of counted pulses reaches a first number; a second flip-flop circuit having an input for receiving the stop signal, a data input, and an output connected to the data input and for providing the low-frequency signal; an inverter having an input for receiving the stop signal; and a second logic gate having a first input connected to an output of said inverter for receiving the stop signal, a second input for receiving the reset signal, and an output connected to said counter for providing a setting signal thereto.

Claim 29

A clock signal generator according to claim 25 , wherein said frequency divider further comprises a third flip-flop circuit connected between said counter and said oscillator for providing a binary number for equal to the number of counted pulses in the high-frequency output signal during a half-period of the reference signal and representing the frequency of the high-frequency clock signal.

Claim 30

A clock signal generator according to claim 26 , wherein said oscillator driving circuit increases a value of the coefficient of proportionality if the binary number is significantly different from a desired number, and reduces the value of the coefficient of proportionality it the binary number is close to the desired number.

Claim 31

A clock signal generator according to claim 26 , wherein said oscillator driving circuit linearly modulates the coefficient of proportionality as a function of a difference between the binary number and a desired number.

Claim 32

A clock signal generator according to claim 26 , wherein said oscillator driving circuit modulates the coefficient of proportionality so that the coefficient of proportionality takes a first value when an absolute value of a difference between the binary number is less than a threshold, otherwise the coefficient of proportionality takes a second value.

Claim 35

A method according to claim 30 , further comprising deactivating the at least one control signal at each leading edge of the reference signal based upon the reset signal.

Claim 36

A method according to claim 30 , wherein providing the reset signal comprises: providing the reference signal to a data input of a first flip-flop circuit, and providing the high-frequency output signal to a second input of the first flip-flop circuit; and performing a logic function using a first logic gate having a first input connected to the data input of the first flip-flop circuit, a second input connected to a data output of the first flip-flop circuit, and an output for providing the reset signal.

Claim 37

A method according to claim 30 , wherein providing the low-frequency signal comprises: counting pulses of the high-frequency signal using a counter for providing a stop signal when a number of counted pulses reaches a first number; using a second flip-flop circuit having an input for receiving the stop signal, a data input, and an output connected to the data input and for providing the low-frequency signal; inverting the stop signal; and using a second logic gate having a first input for receiving an inverted stop signal, a second input for receiving the reset signal, and an output connected to the counter for providing a setting signal thereto.

Claim 38

A method according to claim 33 , wherein a third flip-flop is connected between the counter and the oscillator driving circuit for providing a binary number equal to the number of counted pulses in the high-frequency output signal during a half-period of the reference signal and representing f the frequency of the high-frequency output signal.

Claim 39

A method according to claim 34 , wherein the oscillator driving circuit increases a value of the coefficient of proportionality if the binary number is significantly different from a desired number, and reduces the value of the coefficient of proportionality if the binary number is close to the desired number.

Claim 40

A method according to claim 34 , wherein the oscillator driving circuit linearly modulates the coefficient of proportionality as a function of a difference between the binary number and a desired number.

Claim 41

A method according to claim 34 , wherein the oscillator driving circuit modulates the coefficient of proportionality so that the coefficient of proportionality takes a first value when an absolute value of a difference between the binary number is less than a threshold, otherwise the coefficient of proportionality takes a second value.