Phase lock loop circuit

Claim 2

A phase lock loop circuit for switching a division ratio of a variable divider to carry out a fractional division, comprising: a voltage control oscillator; a variable divider for varying a division ratio of an output of a voltage control oscillator in response to a divider control signal; an operation unit for previously calculating divider control data to obtain a division number corresponding to an output frequency; a divider switching memory circuit for writing the divider control data and reading the data every time an output of the variable divider is generated, to set a division value of the variable divider; a phase comparator for phase comparing the output of the variable divider with a reference frequency; and a low-pass filter for inputting an output of the phase comparator and removing a high frequency component; wherein said voltage control oscillator changes an oscillation frequency through an output of said low-pass filter, and wherein said variable divider switches a division ratio to obtain an average division number (N+L/A), where N, L and A are integers.

Claim 3

The phase lock loop circuit according to claim 1 , wherein said operation unit previously calculates a division value in accordance with a calculation algorithm through ΣΔ (sigma delta) modulation.

Claim 4

A phase lock loop circuit for switching a division ratio of a variable divider to carry out a fractional division, comprising: a voltage control oscillator; a variable divider for varying a division ratio of an output of a voltage control oscillator in response to a divider control signal; an operation unit for previously calculating divider control data to obtain a division number corresponding to an output frequency; a divider switching memory circuit for writing the divider control data and reading the data every time an output of the variable divider is generated, to set a division value of the variable divider; a phase comparator for phase comparing the output of the variable divider with a reference frequency; and a low-pass filter for inputting an output of the phase comparator and removing a high frequency component; wherein said voltage control oscillator changes an oscillation frequency through an output of said low-pass filter, and wherein said divider switching memory circuit writes the divider control data to a memory, counts divider outputs through a counter to set a read address of the memory, and transmits read data to said variable divider, to set a division value.

Claim 5

A phase lock loop circuit for switching a division ratio of a variable divider to carry out a fractional division, comprising: a voltage control oscillator; a variable divider for varying a division ratio of an output of a voltage control oscillator in response to a divider control signal; an operation unit for previously calculating divider control data to obtain a division number corresponding to an output frequency; a divider switching memory circuit for writing the divider control data and reading the data every time an output of the variable divider is generated, to set a division value of the variable divider; a phase comparator for phase comparing the output of the variable divider with a reference frequency; and a low-pass filter for inputting an output of the phase comparator and removing a high frequency component; wherein said voltage control oscillator changes an oscillation frequency through an output of said low-pass filter, and wherein said divider switching memory circuit writes the divider control data to a memory, counts divider outputs through a counter to set a read address of the memory, and transmits read data to said variable divider, to set a division value.

Claim 6

A phase lock loop circuit for switching a division ratio of a variable divider to carry out a fractional division, comprising: a voltage control oscillator; a variable divider for varying a division ratio of an output of a voltage control oscillator in response to a divider control signal; an operation unit for previously calculating divider control data to obtain a division number corresponding to an output frequency; a divider switching memory circuit for writing the divider control data and reading the data every time an output of the variable divider is generated, to set a division value of the variable divider; a phase comparator for phase comparing the output of the variable divider with a reference frequency; and a low-pass filter for inputting an output of the phase comparator and removing a high frequency component; wherein said voltage control oscillator changes an oscillation freciuency through an output of said low-pass filter, and wherein said memory includes a plurality of memory blocks, writes the divider control data having different frequencies to the different memory blocks for the respective frequencies and switches the memory blocks for reading, to change over the frequencies.

Claim 7

A phase lock loop circuit for switching a division ratio of a variable divider to carry out a fractional division, comprising: a voltage control oscillator; a variable divider for varying a division ratio of an output of a voltage control oscillator in response to a divider control signal; an operation unit for previously calculating divider control data to obtain a division number corresponding to an output frequency; a divider switching memory circuit for writing the divider control data and reading the data every time an output of the variable divider is generated, to set a division value of the variable divider; a phase comparator for phase comparing the output of the variable divider with a reference frequency; and a low-pass filter for inputting an output of the phase comparator and removing a high frequency component; wherein said voltage control oscillator changes an oscillation freciuency through an output of said low-pass filter, and wherein said memory includes a plurality of memory blocks, writes the divider control data having different frequencies to the different memory blocks for the respective frequencies and switches the memory blocks for reading, to change over the frequencies.

Claim 8

The phase lock loop circuit according to claim 4 , wherein said operation unit previously calculates a division value in accordance with a calculation algorithm through ΣΔ (sigma delta) modulation.

Claim 9

The phase lock loop circuit according to claim 5 , wherein said operation unit previously calculates a division value in accordance with a calculation algorithm through ΣΔ (sigma delta) modulation.