Patent US6699745B1 successfully refreshed from Google Patents.
US6699745B1
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Capacitor and memory structure and method
Assignee: Texas Instruments Inc
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Filing: 1998-03-27
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Granted: 2004-03-02
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Expires: 2018-03-27
Abstract
Abstract A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.
Inventors
- 👤 Aditi Banerjee
- 👤 Rick L. Wise
- 👤 Darius L. Crenshaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:41
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; Y; Y10; Y10S; Y10S438/00; Y10S438/964
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
37 words
A method of fabricating a rugged polysilicon layer, comprising: (a) forming a layer of hemispherical grain silicon nuclei of thickness about 12 nm; (b) growing said nuclei into grains; and (c) enhancing the shapes of said grains.
Claim 2
Independent Claim
37 words
A method of fabricating a rugged polysilicon layer, comprising: (a) forming a layer of hemispherical grain silicon nuclei of thickness about 12 nm; (b) growing said nuclei into grains; and (c) enhancing the shapes of said grains.
Claim 3
Dependent Claim
23 words
The method of claim 1 , wherein: (a) said layer of nuclei has a nucleation density of about 1.76×10 11 /cm 3 .
References Cited (Backward Citations)
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