Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; gate electrodes of MISFETs formed over said active regions; dummy gate interconnections each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes; and an interlayer insulating film covering said gate electrodes and dummy gate interconnections and including a film planarized by polishing.

Claim 3

A semiconductor integrated circuit device according to claim 1 , wherein: said active regions are defined by said element isolation region.

Claim 4

A semiconductor integrated circuit device according to claim 1 , wherein: said dummy gate interconnections extend over said dummy region and said element isolation insulating film.

Claim 5

A semiconductor integrated circuit device according to claim 1 , further comprising: interconnections each formed above said interlayer insulating film; dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections; and an insulating film covering said interconnections and dummy interconnections, said insulating film including a film planarized by polishing.

Claim 6

A device according to claim 1 , wherein said dummy gate interconnections are formed also in a scribing area.

Claim 7

A device according to claim 1 , wherein each gate electrode constitutes a gate electrode of a selective MISFET of a memory cell of a DRAM.

Claim 8

A semiconductor integrated circuit device according to claim 1 , wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions.

Claim 9

A semiconductor integrated circuit device comprising: an active region and a dummy region of a semiconductor substrate; a semiconductor element formed in said active region; a trench defining said active region and said dummy region; an element isolation insulating film embedded in said trench with an insulating film including a film planarized by polishing; and a gate interconnection formed on said active region and element isolation insulating film; and an element isolation region defining said active region and being comprised of said dummy region and element isolation insulating film, said gate interconnection extending over said element isolation insulating film so as not to extend over said dummy region.

Claim 10

A semiconductor integrated circuit device comprising: an active region and a dummy region of a semiconductor substrate; a semiconductor element formed in said active region; a trench defining said active region and said dummy region; an element isolation insulating film embedded in said trench with an insulating film including a film planarized by polishing; and a gate interconnection formed on said active region and element isolation insulating film; and an element isolation region defining said active region and being comprised of said dummy region and element isolation insulating film, said gate interconnection extending over said element isolation insulating film so as not to extend over said dummy region.

Claim 11

A device according to claim 8 , wherein: a dummy gate interconnection is comprised of a same layer as said gate interconnection, and said dummy gate interconnection is disposed on said dummy region and element isolation insulating film in said element isolation region.

Claim 12

A device according to claim 8 , wherein said dummy region is formed also in a scribing area.

Claim 13

A semiconductor integrated circuit device according to claim 8 , wherein dummy gate interconnections are comprised of a same layer as said gate interconnection and are formed over said element isolation region.

Claim 14

A semiconductor integrated circuit device comprising: interconnections formed on a principal surface of a semiconductor substrate; dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections; and an insulating film covering said interconnections and dummy interconnections and including a film planarized by polishing; said dummy interconnections being formed also in a scribing area, wherein a length of said dummy interconnection is shorter than a distance between bonding pads.

Claim 15

A semiconductor integrated circuit device comprising: interconnections formed on a principal surface of a semiconductor substrate; dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections; and an insulating film covering said interconnections and dummy interconnections and including a film planarized by polishing; said dummy interconnections being formed also in a scribing area, wherein a length of said dummy interconnection is shorter than a distance between bonding pads.

Claim 16

A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface, said principal surface including active areas for MISFETs to be formed and an isolation area for providing a required space between said active areas; a trench pattern formed in said substrate except for said active areas such that a plurality of dummy semiconductor regions separated from each other by said trench pattern are formed at said isolation area, said trench pattern having a selected trench portion and another trench portion, said selected trench portion formed in a portion of said isolation area where a gate interconnection for said elements is to be provided, and said another trench portion formed so as to define active semiconductor regions at said active areas; a first insulating film buried in said trench pattern and formed by polishing an insulating film deposited on said principal surface having said trench pattern; gate insulating films of said MISFETs formed on said active semiconductor regions; gate electrodes of said MISFETs formed on said gate insulating films and formed integrally with said gate interconnections, said gate interconnections electrically coupled between said MISFETs and extending over said selected trench portion; dummy interconnections formed with a same level layer as said gate interconnections and said gate electrodes, said dummy interconnections extending over said dummy semiconductor regions and said another trench portion; and a second insulating film formed over said gate electrodes, said gate interconnections, and said dummy interconnections, said second insulating film formed by polishing an insulating film deposited on said gate electrodes, said gate interconnections, and said dummy interconnections.

Claim 17

A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface, said principal surface including active areas for MISFETs to be formed and an isolation area for providing a required space between said active areas; a trench pattern formed in said substrate except for said active areas such that a plurality of dummy semiconductor regions separated from each other by said trench pattern are formed at said isolation area, said trench pattern having a selected trench portion and another trench portion, said selected trench portion formed in a portion of said isolation area where a gate interconnection for said elements is to be provided, and said another trench portion formed so as to define active semiconductor regions at said active areas; a first insulating film buried in said trench pattern and formed by polishing an insulating film deposited on said principal surface having said trench pattern; gate insulating films of said MISFETs formed on said active semiconductor regions; gate electrodes of said MISFETs formed on said gate insulating films and formed integrally with said gate interconnections, said gate interconnections electrically coupled between said MISFETs and extending over said selected trench portion; dummy interconnections formed with a same level layer as said gate interconnections and said gate electrodes, said dummy interconnections extending over said dummy semiconductor regions and said another trench portion; and a second insulating film formed over said gate electrodes, said gate interconnections, and said dummy interconnections, said second insulating film formed by polishing an insulating film deposited on said gate electrodes, said gate interconnections, and said dummy interconnections.

Claim 18

A semiconductor integrated circuit device according to claim 13 , wherein wiring lines and dummy wiring lines are formed over said second insulating film.

Claim 19

A semiconductor integrated circuit device according to claim 13 , wherein said dummy interconnections are arranged to be regularly repeated at said isolation area.

Claim 20

A semiconductor integrated circuit device according to claim 13 , wherein said dummy interconnections are arranged to be regularly repeated at said isolation area, and wherein dummy semiconductor region interconnections are arranged to be regularly repeated at said isolation area.

Claim 21

A semiconductor integrated circuit device according to claim 13 , wherein said dummy interconnections are under an electrically floating state.

Claim 22

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench with an insulating film planarized by polishing such that said element isolation insulating film serves as an element isolation region; gate electrodes of MISFETs formed over said active regions; dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes; an interlayer insulating film covering said gate electrodes and said dummy patterns and including an insulating film planarized by polishing.

Claim 23

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench with an insulating film planarized by polishing such that said element isolation insulating film serves as an element isolation region; gate electrodes of MISFETs formed over said active regions; dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes; an interlayer insulating film covering said gate electrodes and said dummy patterns and including an insulating film planarized by polishing.

Claim 24

A semiconductor integrated circuit device according to claim 18 , wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions.

Claim 25

A semiconductor integrated circuit device according to claim 19 , wherein said gate interconnection is electrically connected between said gate electrodes of said MISFETs.

Claim 26

A semiconductor integrated circuit device according to claim 19 , wherein said dummy patterns are formed over said element isolation region.

Claim 27

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said active regions and said element isolation insulating film serve as an element isolation region; and gate electrodes of MISFETs formed over said active regions, wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions.

Claim 28

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said active regions and said element isolation insulating film serve as an element isolation region; and gate electrodes of MISFETs formed over said active regions, wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions.

Claim 29

A semiconductor integrated circuit device according to claim 22 , further comprising: dummy patterns each comprised of a same layer as said gate electrodes, formed over said element isolation region, and spaced from said gate electrodes; and an interlayer insulating film covering said gate electrodes and said dummy patterns and including an insulating film planarized by polishing.

Claim 30

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements; and dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes.

Claim 31

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements; and dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes.

Claim 32

A semiconductor integrated circuit device according to claim 24 , further comprising: an interlayer insulating film covering said electrodes and said dummy patterns and including an insulating film planarized by polishing.

Claim 33

A semiconductor integrated circuit device according to claim 24 , wherein said dummy regions and dummy patterns are formed at a scribing area.

Claim 34

A semiconductor integrate circuit device comprising; a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements; and dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes, wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions.

Claim 35

A semiconductor integrate circuit device comprising; a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements; and dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes, wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions.

Claim 36

A semiconductor integrated circuit device according to claim 27 , wherein said dummy regions are formed between said MISFET type elements such that said gate interconnection is formed so as not to extend over said dummy regions.

Claim 37

A semiconductor integrated Circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; wherein said dummy regions are formed at a scribing area.

Claim 38

A semiconductor integrated Circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; wherein said dummy regions are formed at a scribing area.

Claim 39

A semiconductor integrated circuit device according to claim 29 , further comprising: electrodes formed over said active regions and serving as gate electrodes of MISFET type elements; dummy patterns each comprised of a same layer as said electrodes and formed in a region spaced from said electrodes; and an interlayer insulating film covering said electrodes and said dummy patterns and including an insulating film planarized by polishing.

Claim 40

A semiconductor integrated circuit device according to claim 29 , wherein a length of said dummy region is shorter than a distance between bonding pads.

Claim 41

A semiconductor integrated circuit device according to claim 29 , further comprising: interconnections formed over said semiconductor substrate; and dummy interconnections each comprised of a same layer as said interconnections and spaced from said interconnections; and wherein said dummy interconnections are formed at said scribing area.

Claim 42

A semiconductor integrated circuit device according to claim 32 , wherein a length of said dummy region is shorter than a distance between bonding pads.

Claim 43

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; an interlayer insulating film covering said substrate and said dummy regions and including an insulating film planarized; and external terminals formed over said interlayer insulating film, wherein said dummy regions are formed under said external terminals and are formed at said scribing area.

Claim 44

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; an interlayer insulating film covering said substrate and said dummy regions and including an insulating film planarized; and external terminals formed over said interlayer insulating film, wherein said dummy regions are formed under said external terminals and are formed at said scribing area.

Claim 45

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region, wherein said dummy regions are formed at a scribing area; gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements; and dummy patterns each comprised of a same layer as said gate electrodes and spaced from a marker portion for photolithography.

Claim 46

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region, wherein said dummy regions are formed at a scribing area; gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements; and dummy patterns each comprised of a same layer as said gate electrodes and spaced from a marker portion for photolithography.

Claim 47

A semiconductor integrated circuit device according to claim 35 , wherein a length of said dummy pattern is shorter than a distance between said dummy pattern and said marker portion for photolithography.

Claim 48

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region, wherein said dummy regions are formed at a scribing area; interconnections formed over said substrate; and dummy interconnections each comprised of a same layer as said interconnections and spaced from a marker portion for photolithography.

Claim 49

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region, wherein said dummy regions are formed at a scribing area; interconnections formed over said substrate; and dummy interconnections each comprised of a same layer as said interconnections and spaced from a marker portion for photolithography.

Claim 50

A semiconductor integrated circuit device according to claim 37 , wherein a length of said dummy interconnect is shorter than a distance between said dummy interconnect and said marker portion for photolithography.

Claim 51

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region, wherein said dummy regions are formed at a scribing area; interconnections formed over said substrate; and dummy interconnections each comprised of a same layer as said interconnections and formed under external terminals.

Claim 52

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region, wherein said dummy regions are formed at a scribing area; interconnections formed over said substrate; and dummy interconnections each comprised of a same layer as said interconnections and formed under external terminals.

Claim 53

A semiconductor integrated circuit device according to claim 39 , wherein a length of said interconnections is shorter than a distance between said external terminals.

Claim 54

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; and external terminals formed over said substrate, wherein said dummy regions are formed at a scribing area such that a length of said dummy region is shorter than a distance between said external terminals.

Claim 55

A semiconductor integrated circuit device comprising: a trench formed in a semiconductor substrate and defining active regions and dummy regions; an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region; and external terminals formed over said substrate, wherein said dummy regions are formed at a scribing area such that a length of said dummy region is shorter than a distance between said external terminals.

Claim 56

A semiconductor integrated circuit device comprising: interconnections formed over a principal surface of a semiconductor substrate; and dummy interconnections each comprised of a same layer as said interconnections, spaced from said interconnections and formed in a scribe area such that a length of said dummy interconnection is shorter than a distance between external terminals.

Claim 57

A semiconductor integrated circuit device comprising: interconnections formed over a principal surface of a semiconductor substrate; and dummy interconnections each comprised of a same layer as said interconnections, spaced from said interconnections and formed in a scribe area such that a length of said dummy interconnection is shorter than a distance between external terminals.

Claim 58

A semiconductor integrated circuit device according to claim 42 , wherein bump electrodes are formed over said external terminals.

Claim 59

A semiconductor integrated circuit device comprising: interconnections formed over a principal surface of a semiconductor substrate; dummy interconnections each comprised of a same layer as said interconnections and spaced from said interconnections; and external terminals formed over said substrate, wherein said dummy interconnections are formed at a scribing area such that a length of said dummy interconnection is shorter than a distance between said external terminals.

Claim 60

A semiconductor integrated circuit device comprising: interconnections formed over a principal surface of a semiconductor substrate; dummy interconnections each comprised of a same layer as said interconnections and spaced from said interconnections; and external terminals formed over said substrate, wherein said dummy interconnections are formed at a scribing area such that a length of said dummy interconnection is shorter than a distance between said external terminals.

Claim 61

A semiconductor integrated circuit device according to claim 44 wherein bump electrodes are formed over said external terminals.

Claim 62

A semiconductor integrated circuit device comprising: interconnections formed over a principal surface of a semiconductor substrate; dummy interconnections each comprised of a same layer as said interconnections and spaced from said interconnections; an interlayer insulating film covering said interconnections and said dummy interconnections; and external terminals formed over said interlayer insulating film, wherein said dummy interconnections are formed at a scribing area such that a length of said dummy interconnection is shorter than a distance between said external terminals.

Claim 63

A semiconductor integrated circuit device comprising: interconnections formed over a principal surface of a semiconductor substrate; dummy interconnections each comprised of a same layer as said interconnections and spaced from said interconnections; an interlayer insulating film covering said interconnections and said dummy interconnections; and external terminals formed over said interlayer insulating film, wherein said dummy interconnections are formed at a scribing area such that a length of said dummy interconnection is shorter than a distance between said external terminals.

Claim 64

A semiconductor integrated circuit device according to claim 46 , wherein bump electrodes are formed over said external terminals.