US6645842B2
Expired / Lapsed
US
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Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
Assignee: Toshiba Corp
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Filing: 2002-07-18
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Granted: 2003-11-11
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Expires: 2022-07-18
Abstract
Abstract There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility, achieve facility of wiring design, and reduce production cost.The present invention forms an X-Y reference wiring grid using wirings of a total of M (M>=2) layers in which an n-th (n>=2) layer wiring intersects orthogonally with a (n-1)-th layer wiring, and forms an oblique wiring grid which intersects with the reference wiring layer to have an angle of 45 degree or 135 degree is formed by a (m+1)-th layer wiring and a (m+2)-th layer wiring which are intersected orthogonally with each other, such that the (m+1)-th layer wiring and (m+2)-th layer wiring in the oblique wiring grid has a wiring pitch of {square root over (2 times of that of wiring in the reference wiring grid, and also wiring widths of {square root over (2 times of that of wiring in the reference wiring layer.
Inventors
- 👤 Mutsunori Igarashi
- 👤 Takashi Mitsuhashi
- 👤 Masami Murakata
- 👤 Masaaki Yamada
- 👤 Fumihiro Minami
- 👤 Toshihiro Akiyama
- 👤 Takahiro Aoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:11
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10D; H10D89/00; H10W20/43; H10W20/495; H10B; H10B12/00; H10B12/30; H10B12/48
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
163 words
A method of arranging a buffer cell on a multi-layer wiring structured semiconductor circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; forming a wiring path in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at a first arbitrary point in the 45 degrees direction or the 135 degrees direction without going through the other layer; and inserting a buffer cell at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 2
Independent Claim
163 words
A method of arranging a buffer cell on a multi-layer wiring structured semiconductor circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; forming a wiring path in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at a first arbitrary point in the 45 degrees direction or the 135 degrees direction without going through the other layer; and inserting a buffer cell at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 3
Dependent Claim
37 words
The method of claim 1 , wherein a wiring thickness of the 45 degree direction wiring and the 135 degree direction wiring are set {square root over ( )}2 times than the horizontal and vertical direction wirings.
Claim 4
Independent Claim
166 words
A method of arranging a buffer cell on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; forming a wiring path in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at a first arbitrary point in the horizontal direction or the vertical direction without going through the other layer; and inserting a buffer cell at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 5
Independent Claim
166 words
A method of arranging a buffer cell on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; forming a wiring path in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at a first arbitrary point in the horizontal direction or the vertical direction without going through the other layer; and inserting a buffer cell at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 6
Dependent Claim
37 words
The method of claim 3 , wherein a wiring thickness of the 45 degree direction wiring and the 135 degree direction wiring are set {square root over ( )}2 times than the horizontal and vertical direction wirings.
Claim 7
Dependent Claim
168 words
A multi-layer wiring structured semiconductor integrated circuit device containing a buffer cell, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; a wiring path formed in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at a first arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer; and a buffer cell inserted at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 8
Dependent Claim
168 words
A multi-layer wiring structured semiconductor integrated circuit device containing a buffer cell, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; a wiring path formed in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at a first arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer; and a buffer cell inserted at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 9
Dependent Claim
23 words
The multi-layer wiring structured semiconductor integrated circuit according to claim 5 , wherein said wiring layers are comprised of at least five layers.
Claim 10
Dependent Claim
37 words
The device of claim 5 , wherein a wiring thickness of the 45 degree direction wiring and the 135 degree direction wiring are set {square root over ( )}2 times than the horizontal and vertical direction wirings.
Claim 11
Dependent Claim
173 words
A multi-layer wiring method structured semiconductor integrated circuit device containing a buffer cell, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; a wiring path formed in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at a first arbitrary point in the horizontal direction or the vertical direction without going through the other layer; and a buffer cell inserted at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 12
Dependent Claim
173 words
A multi-layer wiring method structured semiconductor integrated circuit device containing a buffer cell, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; a wiring path formed in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at a first arbitrary point in the horizontal direction or the vertical direction without going through the other layer; and a buffer cell inserted at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein the first arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 13
Dependent Claim
23 words
The multi-layer wiring structured semiconductor integrated circuit according to claim 8 , wherein said wiring layers are comprised of at least five layers.
Claim 14
Dependent Claim
37 words
The device of claim 8 , wherein a wiring thickness of the 45 degree direction wiring and the 135 degree direction wiring are set {square root over ( )}2 times than the horizontal and vertical direction wirings.
Claim 15
Independent Claim
154 words
A method of forming a wiring path on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and forming a wiring path in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 16
Independent Claim
154 words
A method of forming a wiring path on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and forming a wiring path in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 17
Independent Claim
157 words
A method of forming a wiring path on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; forming a wiring path in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 18
Independent Claim
157 words
A method of forming a wiring path on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; forming a wiring path in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 19
Dependent Claim
160 words
A multi-layer wiring structured semiconductor integrated circuit device, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and a wiring path formed in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at an arbitrary point in the 45 degrees direction or the 135 degrees direction without going through the other layer, wherein said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 20
Dependent Claim
160 words
A multi-layer wiring structured semiconductor integrated circuit device, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and a wiring path formed in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at an arbitrary point in the 45 degrees direction or the 135 degrees direction without going through the other layer, wherein said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 21
Dependent Claim
23 words
The multi-layer wiring structured semiconductor integrated circuit according to claim 13 , wherein said wiring layers are comprised of at least five layers.
Claim 22
Dependent Claim
162 words
A multi-layer wiring structured semiconductor integrated circuit device, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and a wiring path formed in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 23
Dependent Claim
162 words
A multi-layer wiring structured semiconductor integrated circuit device, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and a wiring path formed in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 24
Dependent Claim
23 words
The multi-layer wiring structured semiconductor integrated circuit according to claim 15 , wherein said wiring layers are comprised of at least five layers.
Claim 25
Independent Claim
148 words
A method of forming a clock tree which supplies a clock signal to a synchronizing circuit on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and forming a clock tree by bending a horizontal direction wiring or a vertical direction wiring thereof in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein said clock tree controls a clock delay in a end thereof, and the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 26
Independent Claim
148 words
A method of forming a clock tree which supplies a clock signal to a synchronizing circuit on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and forming a clock tree by bending a horizontal direction wiring or a vertical direction wiring thereof in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein said clock tree controls a clock delay in a end thereof, and the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 27
Independent Claim
152 words
A method of forming a clock tree which supplies a clock signal to a synchronizing circuit on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and forming a clock tree by bending a 45 degrees direction wiring or a 135 degrees direction wiring thereof in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein said clock tree controls a clock delay in a end thereof, and the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 28
Independent Claim
152 words
A method of forming a clock tree which supplies a clock signal to a synchronizing circuit on a multi-layer wiring structured semiconductor integrated circuit, comprising: forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and forming a clock tree by bending a 45 degrees direction wiring or a 135 degrees direction wiring thereof in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein said clock tree controls a clock delay in a end thereof, and the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 29
Dependent Claim
151 words
A multi-layer wiring structured semiconductor integrated circuit device, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and a clock tree which supplies a clock signal to a synchronizing circuit by bending a horizontal direction wiring or a vertical direction wiring thereof in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein said clock tree controls a clock delay in a end thereof, and the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 30
Dependent Claim
151 words
A multi-layer wiring structured semiconductor integrated circuit device, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and a clock tree which supplies a clock signal to a synchronizing circuit by bending a horizontal direction wiring or a vertical direction wiring thereof in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein said clock tree controls a clock delay in a end thereof, and the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 31
Dependent Claim
23 words
The multi-layer wiring structured semiconductor integrated circuit according to claim 19 , wherein said wiring layers are comprised of at least five layers.
Claim 32
Dependent Claim
155 words
A multi-layer wiring structured semiconductor integrated circuit device, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and a clock tree which supplies a clock signal to a synchronizing circuit by bending a 45 degrees direction wiring or a 135 degrees direction wiring thereof in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein said clock tree controls a clock delay in a end thereof, and the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 33
Dependent Claim
155 words
A multi-layer wiring structured semiconductor integrated circuit device, comprising: a semiconductor area in which a plurality of unit elements are formed; a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer; and a clock tree which supplies a clock signal to a synchronizing circuit by bending a 45 degrees direction wiring or a 135 degrees direction wiring thereof in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein said clock tree controls a clock delay in a end thereof, and the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.
Claim 34
Dependent Claim
23 words
The multi-layer wiring structured semiconductor integrated circuit according to claim 21 , wherein said wiring layers are comprised of at least five layers.
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