Patent US8358355B2 successfully refreshed from Google Patents.
Patent US6621169B2 successfully refreshed from Google Patents.
US6621169B2
Expired / Lapsed
US
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Stacked semiconductor device and method of producing the same
Assignee: Socionext Inc
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Filing: 2001-08-29
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Granted: 2003-09-16
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Expires: 2021-08-29
Abstract
Abstract In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.
Inventors
- 👤 Katsuhito Kikuma
- 👤 Mitsutaka Ikeda
- 👤 Yoshihiro Tsukidate
- 👤 Yuji Akashi
- 👤 Kaname Ozawa
- 👤 Akira Takashima
- 👤 Tadashi Uno
- 👤 Takao Nishimura
- 👤 Fumihiko Ando
- 👤 Hiroshi Onodera
- 👤 Hayato Okuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:23
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W90/00; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/656; H10W72/00; H10W72/01; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/541; H10W72/5445; H10W72/547; H10W72/5473; H10W72/851; H10W72/853; H10W72/859; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W72/941; H10W72/9415; H10W74/15; H10W90/20; H10W90/22; H10W90/24; H10W90/28; H10W90/284; H10W90/291; H10W90/701; H10W90/721; H10W90/722; H10W90/724; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
163 words
A stacked semiconductor device comprising: a first substrate that has external connecting terminals; first terminals that are placed on a surface of the first substrate opposite to a surface of the first substrate on which the external connecting terminals of the first substrate are formed; at least one first semiconductor chip that is mounted on the first substrate; a redistribution layer provided on the first semiconductor chip; at least one second semiconductor chip that is mounted on the redistribution layer; and a third semiconductor chip that is used for testing at least one of the first and second semiconductor chips, the third semiconductor chip being mounted on the redistribution layer and over the first semiconductor chip so as to be in a stacked relationship with the first semiconductor chip, wherein at least one of the first and second semiconductor chip is electrically connected to the first substrate via the redistribution layer, and the third semiconductor chip is electrically connected to the redistribution layer.
Claim 2
Dependent Claim
163 words
A stacked semiconductor device comprising: a first substrate that has external connecting terminals; first terminals that are placed on a surface of the first substrate opposite to a surface of the first substrate on which the external connecting terminals of the first substrate are formed; at least one first semiconductor chip that is mounted on the first substrate; a redistribution layer provided on the first semiconductor chip; at least one second semiconductor chip that is mounted on the redistribution layer; and a third semiconductor chip that is used for testing at least one of the first and second semiconductor chips, the third semiconductor chip being mounted on the redistribution layer and over the first semiconductor chip so as to be in a stacked relationship with the first semiconductor chip, wherein at least one of the first and second semiconductor chip is electrically connected to the first substrate via the redistribution layer, and the third semiconductor chip is electrically connected to the redistribution layer.
Claim 3
Dependent Claim
25 words
The stacked semiconductor device as claimed in claim 1 , wherein the redistribution layer is formed by patterning a copper plate or a copper foil.
Claim 4
Dependent Claim
22 words
The stacked semiconductor device as claimed in claim 1 , wherein the redistribution layer is formed of a flexible printed wiring board.
Claim 5
Dependent Claim
29 words
The stacked semiconductor device as claimed in claim 3 , wherein the flexible printed wiring board is made of a polyimide tape on which a conductive pattern is formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-09-15 | 2007-03-17 | 2007-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-09-15 | 2011-03-17 | 2011-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-09-15 | 2015-03-17 | 2015-09-16 | $7700.00 | Window Closed / Lapsed |