Patent US6620564B2 successfully refreshed from Google Patents.
US6620564B2
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US
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Method for patterning semiconductors through adjustment of image peak side lobes
Assignee: Macronix International Co Ltd
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Filing: 2002-02-01
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Granted: 2003-09-16
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Expires: 2022-02-01
Abstract
Abstract First of all, an adjusting step is performed to change a first optical parameter and a second optical parameter, so as to adjust the positions of two side-lobes of the main feature's exposure peak and overlap with the main feature's exposure peak and two side-lobes thereof, wherein the first optical parameter is the Numerical Aperture (NA) and the second optical parameter is the sigma(σ). Afterward, a lithography process is performed by using a translucent mask to pattern the semiconductor devices, wherein the translucent mask can equalize the intensity of the main feature's exposure peak and the side-lobes thereof from each other. Therefore, this invention can reduce the pitch to decrease the critical dimension of the semiconductor devices.
Inventors
- 👤 Chi-Yuan Hung
- 👤 I-Pien Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:35
CPC Classifications
G; G03; G03F; G03F1/00; G03F1/54; G03F1/50; G03F7/00; G03F7/70; G03F7/70425
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
81 words
A method for forming the exposure peak of the lithography process, the method comprising: providing a first exposure peak of a main feature that is utilized for said lithography process, wherein a side-lobe is beside on the sidewall of said first exposure peak; and performing an adjusting step to change a first optical parameter and a second optical parameter, so as to adjust the position of said side-lobe of said first exposure peak and form a plurality of second exposure peaks.
Claim 2
Independent Claim
81 words
A method for forming the exposure peak of the lithography process, the method comprising: providing a first exposure peak of a main feature that is utilized for said lithography process, wherein a side-lobe is beside on the sidewall of said first exposure peak; and performing an adjusting step to change a first optical parameter and a second optical parameter, so as to adjust the position of said side-lobe of said first exposure peak and form a plurality of second exposure peaks.
Claim 3
Dependent Claim
18 words
The method according to claim 1 , wherein said first optical parameter comprises a Numerical Aperture (NA) parameter.
Claim 4
Dependent Claim
16 words
The method according to claim 1 , wherein said second optical parameter comprises a sigma parameter.
Claim 5
Independent Claim
113 words
A method for patterning the semiconductor devices, the method comprising: providing a first exposure peak of a main feature that is utilized for the lithography process, wherein a side-lobe is beside on the sidewall of said first exposure peak, and said first exposure peak has a first pitch; performing an adjusting step to change a first optical parameter and a second optical parameter, so as to adjust the position of said side-lobe of said first exposure peak and overlap said first exposure peak with said side-lobe thereof; and performing a lithography process by using a halftone mask with said main feature to form a plurality of second exposure peaks with a second pitch.
Claim 6
Independent Claim
113 words
A method for patterning the semiconductor devices, the method comprising: providing a first exposure peak of a main feature that is utilized for the lithography process, wherein a side-lobe is beside on the sidewall of said first exposure peak, and said first exposure peak has a first pitch; performing an adjusting step to change a first optical parameter and a second optical parameter, so as to adjust the position of said side-lobe of said first exposure peak and overlap said first exposure peak with said side-lobe thereof; and performing a lithography process by using a halftone mask with said main feature to form a plurality of second exposure peaks with a second pitch.
Claim 7
Dependent Claim
18 words
The method according to claim 4 , wherein said first optical parameter comprises a Numerical Aperture (NA) parameter.
Claim 8
Dependent Claim
16 words
The method according to claim 4 , wherein said second optical parameter comprises a sigma parameter.
Claim 9
Dependent Claim
20 words
The method according to claim 4 , wherein the transmission of said halftone mask is about between 30% and 50%.
Claim 10
Dependent Claim
22 words
The method according to claim 4 , wherein said halftone mask can equalize the intensity of said plurality of second exposure peaks.
Claim 11
Dependent Claim
17 words
The method according to claim 4 , wherein said second pitch is about half said first pitch.
Claim 12
Independent Claim
211 words
A method for reducing the pitch of the semiconductor devices, the method comprising: providing a semiconductor substrate with a semiconductor layer thereon; forming a photoresist layer on said semiconductor layer; providing a first exposure peak of a main feature with a first width that is utilized for the lithography process, wherein a plurality of side-lobes are individually beside on the sidewalls of said first exposure peak, and said first exposure peak has a first pitch; adjusting a first optical parameter of Numerical Aperture (NA) and a second optical parameter of sigma, so as to adjust the position of said side-lobe of said first exposure peak and overlap said first exposure peak with said side-lobe thereof; performing a lithography process by using a halftone mask with said main feature to form a plurality of second exposure peaks with a second pitch, so as to form a plurality of photoresist regions on said semiconductor layer, wherein said halftone mask equalizes the intensity of said plurality of exposure peaks from each other, and said second pitch is half said first pitch; and performing an etching process by using said plurality of photoresist regions as photoresist masks to etch said semiconductor layer, so as to form a plurality of semiconductor regions with a second width.
Claim 13
Independent Claim
211 words
A method for reducing the pitch of the semiconductor devices, the method comprising: providing a semiconductor substrate with a semiconductor layer thereon; forming a photoresist layer on said semiconductor layer; providing a first exposure peak of a main feature with a first width that is utilized for the lithography process, wherein a plurality of side-lobes are individually beside on the sidewalls of said first exposure peak, and said first exposure peak has a first pitch; adjusting a first optical parameter of Numerical Aperture (NA) and a second optical parameter of sigma, so as to adjust the position of said side-lobe of said first exposure peak and overlap said first exposure peak with said side-lobe thereof; performing a lithography process by using a halftone mask with said main feature to form a plurality of second exposure peaks with a second pitch, so as to form a plurality of photoresist regions on said semiconductor layer, wherein said halftone mask equalizes the intensity of said plurality of exposure peaks from each other, and said second pitch is half said first pitch; and performing an etching process by using said plurality of photoresist regions as photoresist masks to etch said semiconductor layer, so as to form a plurality of semiconductor regions with a second width.
Claim 14
Dependent Claim
19 words
The method according to claim 10 , wherein said first optical parameter of Numerical Aperture (NA) is about 0.6.
Claim 15
Dependent Claim
17 words
The method according to claim 10 , wherein said second optical parameter of sigma is about 0.6.
Claim 16
Dependent Claim
17 words
The method according to claim 10 , wherein the transmission of said halftone mask is about 40%.
Claim 17
Dependent Claim
16 words
The method according to claim 10 , wherein said lithography process comprises a deep ultraviolet process.
Claim 18
Dependent Claim
17 words
The method according to claim 10 , wherein said second width is about half said first width.
References Cited (Backward Citations)
US5792596A
Cited
US6335130B1
Cited
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