Patent US4956702A successfully refreshed from Google Patents.
US6608527B2
Expired / Lapsed
US
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Adaptive radio transceiver with low noise amplification
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2002-07-08
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Granted: 2003-08-19
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Expires: 2022-07-08
Abstract
Abstract An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
Inventors
- 👤 Shervin Moloudi
- 👤 Maryam Rofougaran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:16
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/38; H04B1/40; H03; H03B; H03B21/00; H03B21/01; H03B27/00; H03H; H03H11/00; H03H11/02; H03H11/04; H03H11/12; H03H11/1291; H03H21/00; H03H21/0001; H03H21/0012; H04B1/06; H04B1/16; H04B1/30; H04B17/00; H04B17/10; H04B17/101; H04B17/104; H04B17/11; H04B17/14; H04B17/15; H04B17/19; H03H2011/0494; H03J; H03J2200/00; H03J2200/10
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
70 words
A circuit, comprising: a T-network comprising a plurality of series capacitors and at least one shunt inductor; a first transistor coupled to the T-network; a second transistor coupled to the T-network; a third transistor coupled to the first transistor; a fourth transistor coupled to the second transistor; at least one first output inductor coupled to the third transistor; and at least one second output inductor coupled to the fourth transistor.
Claim 2
Dependent Claim
70 words
A circuit, comprising: a T-network comprising a plurality of series capacitors and at least one shunt inductor; a first transistor coupled to the T-network; a second transistor coupled to the T-network; a third transistor coupled to the first transistor; a fourth transistor coupled to the second transistor; at least one first output inductor coupled to the third transistor; and at least one second output inductor coupled to the fourth transistor.
Claim 3
Dependent Claim
17 words
The circuit of claim 1 wherein the first, second, third and fourth transistors comprise field effect transistors.
Claim 4
Dependent Claim
12 words
The circuit of claim 1 wherein the circuit comprises an integrated circuit.
Claim 5
Dependent Claim
13 words
The circuit of claim 1 wherein the circuit comprises an low noise amplifier.
Claim 6
Dependent Claim
72 words
A circuit, comprising: a T-network comprising a plurality of series capacitors and at least one shunt inductor; a first cascode transistor stage coupled to the T-network and comprising a first output node; a second cascode transistor stage coupled to the T-network and comprising a second output node; at least one first output inductor coupled to the first output node; and at least one second output inductor coupled to the second output node.
Claim 7
Dependent Claim
72 words
A circuit, comprising: a T-network comprising a plurality of series capacitors and at least one shunt inductor; a first cascode transistor stage coupled to the T-network and comprising a first output node; a second cascode transistor stage coupled to the T-network and comprising a second output node; at least one first output inductor coupled to the first output node; and at least one second output inductor coupled to the second output node.
Claim 8
Dependent Claim
17 words
The circuit of claim 5 wherein the first and second cascode transistor stages comprise field effect transistors.
Claim 9
Dependent Claim
12 words
The circuit of claim 5 wherein the circuit comprises an integrated circuit.
Claim 10
Dependent Claim
13 words
The circuit of claim 5 wherein the circuit comprises an low noise amplifier.
Claim 11
Independent Claim
54 words
A method of converting a single-ended input signal to a differential signal, comprising: receiving a single-ended input signal at a T-network; sending the single-ended input signal from the T-network to a pair of cascode transistor stages; and generating, by the pair of cascode transistor stages, complementary output signals through a pair of load inductors.
Claim 12
Independent Claim
54 words
A method of converting a single-ended input signal to a differential signal, comprising: receiving a single-ended input signal at a T-network; sending the single-ended input signal from the T-network to a pair of cascode transistor stages; and generating, by the pair of cascode transistor stages, complementary output signals through a pair of load inductors.
Claim 13
Dependent Claim
28 words
The method of claim 9 further comprising tuning the matching circuit for different frequencies by adjusting at least one value of at least one component in the T-network.
Claim 14
Dependent Claim
29 words
The method of claim 9 further comprising tuning the matching circuit for different source impedances by adjusting at least one value of at least one component in the T-network.
References Cited (Backward Citations)
US3909527A
Cited
US4055807A
Cited
US4283739A
Cited
US4315227A
Cited
US4916411A
Cited
US5283484A
Cited
US5404050A
Cited
US5412351A
Cited
US5590412A
Cited
US5574986A
Cited
US5375257A
Cited
US5559475A
Cited
US5878331A
Cited
US5736903A
Cited
US6308047B1
Cited
US5778306A
Cited
US5878089A
Cited
US6016422A
Cited
US6006112A
Cited
US6134430A
Cited
US5945878A
Cited
US6094108A
Cited
US6150901A
Cited
US6160449A
Cited
US6441688B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-08-18 | 2007-02-17 | 2007-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-08-18 | 2011-02-17 | 2011-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-08-18 | 2015-02-17 | 2015-08-19 | $7700.00 | Window Closed / Lapsed |