Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer

Claim 2

A damascene method for forming a patterned conductor layer comprising: providing a substrate; forming over the substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer.

Claim 3

A damascene method for forming a patterned conductor layer comprising: providing a substrate; forming over the substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer, wherein the patterned hard mask layer provides for attenuated abrasive damage to the dielectric layer when forming into the aperture the patterned conductor layer while employing the damascene method.

Claim 4

A damascene method for forming a patterned conductor layer comprising: providing a substrate; forming over the substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer, wherein the patterned hard mask layer provides for attenuated abrasive damage to the dielectric layer when forming into the aperture the patterned conductor layer while employing the damascene method.

Claim 5

The method of claim 1 wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications.

Claim 6

The method of claim 1 wherein the comparatively low dielectric constant dielectric material is selected from the group consisting of spin-on-glass (SOG) dielectric materials, spin-on-polymer (SOP) dielectric materials, nanoporous dielectric materials, amorphous carbon dielectric materials and fluorosilicate glass dielectric materials.

Claim 7

A damascene method for forming a patterned conductor layer comprising: providing a substrate; forming over the substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer, wherein the comparatively low dielectric constant dielectric material is formed employing the same organosilane carbon and silicon source material as the patterned hard mask layer, to provide the dielectric layer graded with the patterned hard mask layer.

Claim 8

A damascene method for forming a patterned conductor layer comprising: providing a substrate; forming over the substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer, wherein the comparatively low dielectric constant dielectric material is formed employing the same organosilane carbon and silicon source material as the patterned hard mask layer, to provide the dielectric layer graded with the patterned hard mask layer.

Claim 9

The method of claim 1 wherein the dielectric layer is formed to a thickness of from about 2000 to about 9000 angstroms.

Claim 10

A damascene method for forming a patterned conductor layer comprising: providing a substrate; forming over the substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a nitrogen and carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer.

Claim 11

A damascene method for forming a patterned conductor layer comprising: providing a substrate; forming over the substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a nitrogen and carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer.

Claim 12

The method of claim 1 wherein the patterned hard mask layer is formed to a thickness of from about 300 to about 900 angstroms.

Claim 13

A damascene method for forming a patterned conductor layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a semiconductor substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter semiconductor substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer.

Claim 14

A damascene method for forming a patterned conductor layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a semiconductor substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter semiconductor substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer.

Claim 15

A damascene method for forming a patterned conductor layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a semiconductor substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter semiconductor substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer, wherein the patterned hard mask layer provides for attenuated abrasive damage to the dielectric layer when forming into the aperture the patterned conductor layer while employing the damascene method.

Claim 16

A damascene method for forming a patterned conductor layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a semiconductor substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter semiconductor substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer, wherein the patterned hard mask layer provides for attenuated abrasive damage to the dielectric layer when forming into the aperture the patterned conductor layer while employing the damascene method.

Claim 17

The method of claim 9 wherein the comparatively low dielectric constant dielectric material is selected from the group consisting of spin-on-glass (SOG) dielectric materials, spin-on-polymer (SOP) dielectric materials, nanoporous dielectric materials, amorphous carbon dielectric materials and fluorosilicate glass dielectric materials.

Claim 18

A damascene method for forming a patterned conductor layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a semiconductor substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter semiconductor substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer, wherein the comparatively low dielectric constant dielectric material is formed employing the same organosilane carbon and silicon source material as the patterned hard mask layer, to provide the dielectric layer graded with the patterned hard mask layer.

Claim 19

A damascene method for forming a patterned conductor layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a semiconductor substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter semiconductor substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer, wherein the comparatively low dielectric constant dielectric material is formed employing the same organosilane carbon and silicon source material as the patterned hard mask layer, to provide the dielectric layer graded with the patterned hard mask layer.

Claim 20

The method of claim 9 wherein the dielectric layer is formed to a thickness of from about 2000 to about 9000 angstroms.

Claim 21

A damascene method for forming a patterned conductor layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a nitrogen and carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a semiconductor substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter semiconductor substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer.

Claim 22

A damascene method for forming a patterned conductor layer comprising: providing a semiconductor substrate; forming over the semiconductor substrate a dielectric layer, the dielectric layer being formed of a comparatively low dielectric constant dielectric material; forming upon the dielectric layer a patterned hard mask layer, the patterned hard mask layer being formed of a nitrogen and carbon doped silicon oxide material formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a semiconductor substrate temperature of from about 200 to about 500 degrees centigrade and a radio frequency deposition power of from about 100 to about 500 watts per square centimeter semiconductor substrate area; etching the dielectric layer to form therein an aperture while employing at least the patterned hard mask layer as an etch mask layer; and forming into the aperture a patterned conductor layer while employing a damascene method which employs the patterned hard mask layer as a planarizing stop layer.

Claim 23

The method of claim 9 wherein the patterned hard mask layer is formed to a thickness of from about 300 to about 700 angstroms.