Patent US6600352B2 successfully refreshed from Google Patents.
US6600352B2
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US
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Timing signal generating circuit
Assignee: Socionext Inc
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Filing: 2000-04-06
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Granted: 2003-07-29
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Expires: 2020-04-06
Abstract
Abstract A circuit, which may be used in a delayed lock loop (DLL) circuit of a semiconductor memory device, for generating a timing signal includes an active circuit, a passive circuit, and a signal transition accelerating circuit. The active circuit sets a first voltage level of the timing signal in response to a clock signal. The passive circuit sets a second voltage level of the timing signal. The signal transition accelerating circuit accelerates transition of the timing signal from the first voltage level to the second voltage level, e.g., from a high level to a low level.
Inventors
- 👤 Yoshikazu Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:34
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; H; H03; H03K; H03K17/00; H03K17/28; G11C7/1066; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
126 words
A DLL circuit for generating an internal clock signal, wherein the DLL circuit comprises: a determination circuit for comparing a timing signal with an external clock signal to generate a comparison signal; a delay circuit for delaying the external clock signal and generating the internal clock signal in accordance with the comparison signal generated by the determination circuit; and a pseudo interface circuit for receiving the internal clock signal and generating the timing signal, wherein the pseudo interface circuit comprises: an active circuit coupled between a high potential power supply and an output node; a passive circuit including one or more resistors coupled to the output node; and a signal transition accelerating circuit connected to the passive circuit, wherein the output node provides the timing signal.
Claim 2
Dependent Claim
126 words
A DLL circuit for generating an internal clock signal, wherein the DLL circuit comprises: a determination circuit for comparing a timing signal with an external clock signal to generate a comparison signal; a delay circuit for delaying the external clock signal and generating the internal clock signal in accordance with the comparison signal generated by the determination circuit; and a pseudo interface circuit for receiving the internal clock signal and generating the timing signal, wherein the pseudo interface circuit comprises: an active circuit coupled between a high potential power supply and an output node; a passive circuit including one or more resistors coupled to the output node; and a signal transition accelerating circuit connected to the passive circuit, wherein the output node provides the timing signal.
Claim 3
Dependent Claim
37 words
The circuit according to claim 1 , wherein the active circuit includes a MOS transistor coupled between the high potential power supply and the output node and the passive circuit includes a resistance dividing circuit comprises resistors.
Claim 4
Dependent Claim
22 words
The circuit according to claim 1 , wherein the pseudo interface circuit further includes an adjustment circuit connected to the passive circuit.
Claim 5
Dependent Claim
33 words
The circuit according to claim 1 , wherein the pseudo interface circuit further includes a control circuit connected to the passive circuit to selectively provide the passive circuit with a power supply voltage.
Claim 6
Dependent Claim
25 words
The circuit according to claim 4 , wherein the control circuit includes a switch connected between the passive circuit and the high potential power supply.
Claim 7
Dependent Claim
54 words
The circuit according to claim 4 , wherein the control circuit includes a first switch connected between the passive circuit and the high potential power supply, a second switch connected between the passive circuit and a low potential power supply, and an inverter connected between the control terminals of the first and second switches.
Claim 8
Dependent Claim
37 words
The circuit according to claim 1 , wherein the signal transition accelerating circuit includes a capacitor having a first terminal connected to the active and passive circuits and a second terminal for receiving a discharge enable signal.
Claim 9
Dependent Claim
192 words
A semiconductor device coupled to an external interface circuit, the semiconductor device comprising: a delay locked loop (DLL) circuit for generating an internal clock signal, wherein the DLL circuit comprises: a determination circuit for comparing a timing signal with an external clock signal to generate a comparison signal; a delay circuit for delaying the external clock signal and generating the internal clock signal in accordance with the comparison signal generated by the determination circuit; and a pseudo interface circuit for receiving the internal clock signal and generating the timing signal, wherein the pseudo interface circuit comprises: an active circuit coupled between a high potential power supply and an output node; a passive circuit including one or more resistors coupled to the output node and; a signal transition accelerating circuit connected to the passive circuit wherein the output node provides the timing signal; a memory circuit block coupled to the DLL circuit; and a data output buffer circuit coupled to the DLL circuit and the memory circuit block, wherein the data output buffer circuit transmits signal from the memory circuit block in accordance with the internal clock signal to the external interface circuit.
Claim 10
Dependent Claim
192 words
A semiconductor device coupled to an external interface circuit, the semiconductor device comprising: a delay locked loop (DLL) circuit for generating an internal clock signal, wherein the DLL circuit comprises: a determination circuit for comparing a timing signal with an external clock signal to generate a comparison signal; a delay circuit for delaying the external clock signal and generating the internal clock signal in accordance with the comparison signal generated by the determination circuit; and a pseudo interface circuit for receiving the internal clock signal and generating the timing signal, wherein the pseudo interface circuit comprises: an active circuit coupled between a high potential power supply and an output node; a passive circuit including one or more resistors coupled to the output node and; a signal transition accelerating circuit connected to the passive circuit wherein the output node provides the timing signal; a memory circuit block coupled to the DLL circuit; and a data output buffer circuit coupled to the DLL circuit and the memory circuit block, wherein the data output buffer circuit transmits signal from the memory circuit block in accordance with the internal clock signal to the external interface circuit.
Claim 11
Dependent Claim
38 words
The DLL circuit according to claim 8 , wherein the active circuit includes a MOS transistor coupled between the high potential power supply and the output node and the passive circuit includes a resistance dividing circuit comprises resistors.
Claim 12
Dependent Claim
23 words
The DLL circuit according to claim 9 , wherein the pseudo interface circuit further includes an adjustment circuit connected to the passive circuit.
Claim 13
Dependent Claim
34 words
The DLL circuit according to claim 8 , wherein the pseudo interface circuit further includes a control circuit connected to the passive circuit to selectively provide the passive circuit with a power supply voltage.
Claim 14
Dependent Claim
26 words
The DLL circuit according to claim 11 , wherein the control circuit includes a switch connected between the passive circuit and the high potential power supply.
Claim 15
Dependent Claim
55 words
The DLL circuit according to claim 11 , wherein the control circuit includes a first switch connected between the passive circuit and the high potential power supply, a second switch connected between the passive circuit and a low potential power supply, and an inverter connected between the control terminals of the first and second switches.
Claim 16
Dependent Claim
38 words
The DLL circuit according to claim 8 , wherein the signal transition accelerating circuit includes a capacitor having a first terminal connected to the active and passive circuits and a second terminal for receiving a discharge enable signal.
Claim 17
Dependent Claim
184 words
A semiconductor memory device, comprising: a delay locked loop (DLL) circuit for generating an internal clock signal, wherein the DLL circuit comprises: a determination circuit for comparing a timing signal with an external clock signal to generate a comparison signal; a delay circuit for delaying the external clock signal and generating the internal clock signal in accordance with the comparison signal generated by the determination circuit; and a pseudo interface circuit for receiving the internal clock signal and generating the timing signal, wherein the pseudo interface circuit comprises: an active circuit coupled between a high potential power supply and an output node; a passive circuit including one or more resistors coupled to the output node; and a signal transition accelerating circuit connected to the passive circuit wherein the output node provides the timing signal; a memory circuit block coupled to the DLL circuit; and a data output buffer circuit coupled to the DLL circuit and the memory circuit block, wherein the data output buffer circuit transmits signal from the memory circuit block in accordance with the internal clock signal to the external interface circuit.
Claim 18
Dependent Claim
184 words
A semiconductor memory device, comprising: a delay locked loop (DLL) circuit for generating an internal clock signal, wherein the DLL circuit comprises: a determination circuit for comparing a timing signal with an external clock signal to generate a comparison signal; a delay circuit for delaying the external clock signal and generating the internal clock signal in accordance with the comparison signal generated by the determination circuit; and a pseudo interface circuit for receiving the internal clock signal and generating the timing signal, wherein the pseudo interface circuit comprises: an active circuit coupled between a high potential power supply and an output node; a passive circuit including one or more resistors coupled to the output node; and a signal transition accelerating circuit connected to the passive circuit wherein the output node provides the timing signal; a memory circuit block coupled to the DLL circuit; and a data output buffer circuit coupled to the DLL circuit and the memory circuit block, wherein the data output buffer circuit transmits signal from the memory circuit block in accordance with the internal clock signal to the external interface circuit.
Claim 19
Dependent Claim
37 words
The device according to claim 15 , wherein the active circuit includes a MOS transistor coupled between the high potential power supply and the output node and the passive circuit includes a resistance dividing circuit comprises resistors.
Claim 20
Dependent Claim
22 words
The device according to claim 16 , wherein the pseudo interface circuit further includes an adjustment circuit connected to the passive circuit.
Claim 21
Dependent Claim
33 words
The device according to claim 15 , wherein the pseudo interface circuit further includes a control circuit connected to the passive circuit to selectively provide the passive circuit with a power supply voltage.
Claim 22
Dependent Claim
25 words
The device according to claim 18 , wherein the control circuit includes a switch connected between the passive circuit and the high potential power supply.
Claim 23
Dependent Claim
54 words
The device according to claim 18 , wherein the control circuit includes a first switch connected between the passive circuit and the high potential power supply, a second switch connected between the passive circuit and a low potential power supply, and an inverter connected between the control terminals of the first and second switches.
Claim 24
Dependent Claim
37 words
The device according to claim 15 , wherein the signal transition accelerating circuit includes a capacitor having a first terminal connected to the active and passive circuits and a second terminal for receiving a discharge enable signal.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-07-28 | 2007-01-27 | 2007-07-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-07-28 | 2011-01-27 | 2011-07-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-07-28 | 2015-01-27 | 2015-07-29 | $7700.00 | Window Closed / Lapsed |