Patent US6593191B2 successfully refreshed from Google Patents.
US6593191B2
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Buried channel strained silicon FET using a supply layer created through ion implantation
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 2001-05-16
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Granted: 2003-07-15
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Expires: 2021-05-16
Abstract
Abstract A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supply can be ion implanted in either the SiGe cap layer or the relaxed SiGe layer. In another embodiment, there is provided a method of fabricating a circuit including providing at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET on a substrate, and ion implanting a dopant supply in the depletion mode FET.
Inventors
- 👤 Eugene A. Fitzgerald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/015; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/60; H10D30/637; H10D30/67; H10D30/674; H10D30/6741; H10D30/6748; H10D30/751; H10D30/791; H10D30/798; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8311; H10D84/84; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S438/00; Y10S438/933
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
75 words
A method of fabricating a buried channel FET, the method comprising the steps of: providing a relaxed SiGe layer on a substrate; providing a channel layer adjacent said relaxed SiGe layer; providing a SiGe cap layer adjacent said channel layer; and ion implanting a dopant supply in at least one of the relaxed SiGe layer and the SiGe cap layer so as to extend along said channel at least between source and drain regions thereof.
Claim 2
Independent Claim
75 words
A method of fabricating a buried channel FET, the method comprising the steps of: providing a relaxed SiGe layer on a substrate; providing a channel layer adjacent said relaxed SiGe layer; providing a SiGe cap layer adjacent said channel layer; and ion implanting a dopant supply in at least one of the relaxed SiGe layer and the SiGe cap layer so as to extend along said channel at least between source and drain regions thereof.
Claim 3
Dependent Claim
11 words
The method of claim 1 , wherein the substrate comprises Si.
Claim 4
Dependent Claim
17 words
The method of claim 1 , wherein the substrate comprises relaxed graded composition SiGe layers on Si.
Claim 5
Dependent Claim
18 words
The method of claim 1 , wherein the substrate comprises Si with a layer of SiO 2 .
Claim 6
Dependent Claim
11 words
The method of claim 1 further comprising forming a metal-oxide-semiconductor gate.
Claim 7
Dependent Claim
18 words
The method of claim 1 , wherein the ion implanted dopant supply is in the SiGe cap layer.
Claim 8
Dependent Claim
18 words
The method of claim 1 , wherein the ion implanted dopant supply is in the relaxed SiGe layer.
Claim 9
Dependent Claim
14 words
The method of claim 1 , wherein the channel layer is under tensile strain.
Claim 10
Dependent Claim
14 words
The method of claim 1 , wherein the channel layer is under compressive strain.
Claim 11
Dependent Claim
20 words
The method of claim 1 , wherein the ion implanted dopant supply comprises As, P, Sb, B, Ga, or In.
Claim 12
Dependent Claim
20 words
The method of claim 8 , wherein the relaxed SiGe layer has a Ge concentration in the range of 10-50%.
Claim 13
Dependent Claim
12 words
The method of claim 11 , wherein the channel layer comprises Si.
Claim 14
Dependent Claim
17 words
The method of claim 12 , wherein the ion implanted dopant supply comprises P, As, or Sb.
Claim 15
Dependent Claim
20 words
The method of claim 9 , wherein the relaxed SiGe layer has a Ge concentration in the range of 50-90%.
Claim 16
Dependent Claim
12 words
The method of claim 14 , wherein the channel layer comprises Ge.
Claim 17
Dependent Claim
17 words
The method of claim 15 , wherein the ion implanted dopant supply comprises B, Ga, or In.
Claim 18
Dependent Claim
18 words
The method of claim 1 , wherein the channel layer has a thickness between 2 and 30 nm.
Claim 19
Dependent Claim
19 words
The method of claim 1 , wherein the SiGe cap layer has a thickness between 2 and 20 nm.
Claim 20
Dependent Claim
11 words
The method of claim 1 further comprising forming an integrated circuit.
Claim 21
Dependent Claim
13 words
The method of claim 1 further comprising interconnecting to a surface channel FET.
Claim 22
Independent Claim
84 words
A method of fabricating a buried channel MOSFET, the method comprising the steps of: providing a relaxed SiGe layer on a substrate; providing a channel layer adjacent said relaxed SiGe layer; providing a SiGe cap layer adjacent said channel layer; providing a gate dielectric above said SiGe cap layer; and ion implanting a dopant supply in at least one of the SiGe cap layer and the relaxed SiGe layer so as to extend along said channel at least between source and drain regions thereof.
Claim 23
Independent Claim
84 words
A method of fabricating a buried channel MOSFET, the method comprising the steps of: providing a relaxed SiGe layer on a substrate; providing a channel layer adjacent said relaxed SiGe layer; providing a SiGe cap layer adjacent said channel layer; providing a gate dielectric above said SiGe cap layer; and ion implanting a dopant supply in at least one of the SiGe cap layer and the relaxed SiGe layer so as to extend along said channel at least between source and drain regions thereof.
Claim 24
Dependent Claim
11 words
The method of claim 21 , wherein the substrate comprises Si.
Claim 25
Dependent Claim
17 words
The method of claim 21 , wherein the substrate comprises relaxed graded composition SiGe layers on Si.
Claim 26
Dependent Claim
18 words
The method of claim 21 , wherein the substrate comprises Si with a layer of SiO 2 .
Claim 27
Dependent Claim
20 words
The method of claim 21 , wherein the relaxed SiGe layer has a Ge composition in the range of 10-50%.
Claim 28
Dependent Claim
12 words
The method of claim 25 , wherein the channel layer comprises Si.
Claim 29
Dependent Claim
17 words
The method of claim 26 , wherein the ion implanted dopant supply comprises P, As, or Sb.
Claim 30
Dependent Claim
11 words
The method of claim 21 further comprising forming an integrated circuit.
Claim 31
Dependent Claim
13 words
The method of claim 21 further comprising interconnecting to a surface channel MOSFET.
Claim 32
Independent Claim
68 words
A method of fabricating a circuit comprising: providing at least one strained channel, enhancement mode FET and at least one strained channel, depletion mode FET on a substrate, the FETs each comprising a source and a drain; and ion implanting a dopant supply in said depletion mode FET, the dopant supply spanning said channel at least between said depletion mode FET source and said depletion mode FET drain.
Claim 33
Independent Claim
68 words
A method of fabricating a circuit comprising: providing at least one strained channel, enhancement mode FET and at least one strained channel, depletion mode FET on a substrate, the FETs each comprising a source and a drain; and ion implanting a dopant supply in said depletion mode FET, the dopant supply spanning said channel at least between said depletion mode FET source and said depletion mode FET drain.
Claim 34
Dependent Claim
14 words
The method of claim 30 , wherein the enhancement mode FET is a MOSFET.
Claim 35
Dependent Claim
14 words
The method of claim 30 , wherein the depletion mode FET is a MOSFET.
Claim 36
Dependent Claim
16 words
The method of claim 30 , wherein the enhancement mode FET is a surface channel MOSFET.
Claim 37
Dependent Claim
16 words
The method of claim 33 , wherein the depletion mode FET is a buried channel MOSFET.
Claim 38
Dependent Claim
16 words
The method of claim 30 , wherein the depletion mode FET is a surface channel MOSFET.
Claim 39
Dependent Claim
16 words
The method of claim 30 , wherein the enhancement mode FET is a buried channel MOSFET.
Claim 40
Dependent Claim
16 words
The method of claim 30 , wherein the depletion mode FET is a buried channel MOSFET.
Claim 41
Dependent Claim
12 words
The method of claim 30 , wherein the circuit is an inverter.
Claim 42
Dependent Claim
22 words
The method of claim 30 , wherein the enhancement mode FET and the depletion mode FET are interconnected to form an inverter.
Claim 43
Independent Claim
69 words
A method of fabricating an inverter comprising: providing a strained buried channel depletion mode FET and a strained surface channel enhancement mode FET on a substrate, the FETs each comprising a source and a drain; and ion implanting a dopant supply in said strained buried channel depletion mode FET, the dopant supply spanning said channel at least between said depletion mode FET source and said depletion mode FET drain.
Claim 44
Independent Claim
69 words
A method of fabricating an inverter comprising: providing a strained buried channel depletion mode FET and a strained surface channel enhancement mode FET on a substrate, the FETs each comprising a source and a drain; and ion implanting a dopant supply in said strained buried channel depletion mode FET, the dopant supply spanning said channel at least between said depletion mode FET source and said depletion mode FET drain.
Claim 45
Dependent Claim
11 words
The method of claim 40 further comprising forming an integrated circuit.
Claim 46
Independent Claim
40 words
A method of fabricating an inverter comprising: providing a strained buried channel depletion mode MOSFET and a strained surface channel enhancement mode MOSFET on a substrate; and ion implanting a dopant supply in said strained buried channel depletion mode MOSFET.
Claim 47
Independent Claim
40 words
A method of fabricating an inverter comprising: providing a strained buried channel depletion mode MOSFET and a strained surface channel enhancement mode MOSFET on a substrate; and ion implanting a dopant supply in said strained buried channel depletion mode MOSFET.
Claim 48
Dependent Claim
11 words
The method of claim 42 further comprising forming an integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-07-14 | 2007-01-13 | 2007-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-07-14 | 2011-01-13 | 2011-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-07-14 | 2015-01-13 | 2015-07-15 | $7700.00 | Window Closed / Lapsed |