US6590815B2
Expired / Lapsed
US
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Semiconductor memory device and method for its test
Assignee: Longitude Licensing Ltd
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Filing: 2001-10-12
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Granted: 2003-07-08
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Expires: 2021-10-12
Abstract
Abstract A semiconductor memory device and method for its test is disclosed including a CBR (CAS before RAS) refresh test achieved by inputting a CBR command for every redundant word line to be selected. In this way, redundant word lines may be selected without repetition until all of the redundant word lines have been selected. By doing so, an accurate determination of the refresh period may be obtained. A CBR refresh counter ( 15 ) may be activated every time a control signal is received when a refresh test on redundant memory cells (RC) is performed. Redundant counter signals (RCNT 0 to RCNT 5 ) may be applied to a X address buffer ( 2 A). X address buffer ( 2 A) may select the redundant counter signals (RCNT 0 to RCNT 5 ) to sequentially select the redundant word lines (RWL 0 to RWL 63 ) when a redundant refresh test is performed.
Inventors
- 👤 Koji Mine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:27
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/783; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C29/02; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/24; G11C29/50; G11C29/50016; G11C2029/0403; G11C29/72
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
94 words
A semiconductor memory device, comprising: a memory cell array including a plurality of normal word lines and a plurality of redundant word lines wherein each of the plurality of redundant word lines are programmable to replace a defective one of the plurality of normal word lines; a test circuit that generates redundant word line selection signals so that the plurality of redundant word lines are sequentially selected without a repeat selection of the same one of the plurality of redundant word lines until all of the plurality of redundant word lines have been selected.
Claim 2
Dependent Claim
94 words
A semiconductor memory device, comprising: a memory cell array including a plurality of normal word lines and a plurality of redundant word lines wherein each of the plurality of redundant word lines are programmable to replace a defective one of the plurality of normal word lines; a test circuit that generates redundant word line selection signals so that the plurality of redundant word lines are sequentially selected without a repeat selection of the same one of the plurality of redundant word lines until all of the plurality of redundant word lines have been selected.
Claim 3
Dependent Claim
63 words
The semiconductor memory device according to claim 1 , wherein: the test circuit includes a counter for generating an address by executing a counting operation every time a count command is received when normal word lines are selected and a redundancy counter for generating a redundant address by executing counting every time a count command is received when redundant word lines are selected.
Claim 4
Dependent Claim
29 words
The semiconductor memory device of claim 2 , wherein: the count command is a CAS before RAS command and the semiconductor memory device is a dynamic random access memory.
Claim 5
Dependent Claim
48 words
The semiconductor memory device of claim 1 , wherein: the test circuit includes a counter incrementing an address when a count command is received and an address buffer rearranging the order of the address depending on whether a redundant word line or a normal word line is selected.
Claim 6
Dependent Claim
29 words
The semiconductor memory device of claim 4 , wherein: the address buffer includes a selector for switching the order of the address when a redundant test signal is activated.
Claim 7
Dependent Claim
41 words
The semiconductor memory device of claim 1 , wherein: the semiconductor memory device is a dynamic random access memory; and the test circuit is coupled to receive a redundant test signal being activated when a redundant refresh test command is received.
Claim 8
Independent Claim
146 words
A method for performing a refresh test in a semiconductor memory device having a plurality of normal word lines and a plurality of redundant word lines, comprising the steps of: generating an address wherein a test address output circuit sequentially generates the address for each normal word line; sequentially activating the plurality of normal word lines based on the address generated to refresh memory cells electrically connected to the activated normal word line; generating a redundant address wherein the test address output circuit sequentially generates the redundant address for each redundant word line; and sequentially activating the plurality of redundant word lines based on the redundant address generated to refresh redundant memory cells electrically connected to the activated redundant word line without a repeat activation of any of the plurality of redundant word lines until all of the plurality of redundant word lines have been activated.
Claim 9
Independent Claim
146 words
A method for performing a refresh test in a semiconductor memory device having a plurality of normal word lines and a plurality of redundant word lines, comprising the steps of: generating an address wherein a test address output circuit sequentially generates the address for each normal word line; sequentially activating the plurality of normal word lines based on the address generated to refresh memory cells electrically connected to the activated normal word line; generating a redundant address wherein the test address output circuit sequentially generates the redundant address for each redundant word line; and sequentially activating the plurality of redundant word lines based on the redundant address generated to refresh redundant memory cells electrically connected to the activated redundant word line without a repeat activation of any of the plurality of redundant word lines until all of the plurality of redundant word lines have been activated.
Claim 10
Dependent Claim
59 words
The method for performing a refresh test of claim 7 , wherein: generating the address includes counting every time a count command is received to sequentially generate the address for each normal word line; and generating the redundant address includes counting every time a count command is received to sequentially generate the redundant address for each redundant word line.
Claim 11
Dependent Claim
32 words
The method for performing a refresh test of claim 8 , wherein: the count command is a CAS before RAS command; and the semiconductor memory device is a dynamic random access memory.
Claim 12
Dependent Claim
36 words
The method for performing a refresh test of claim 7 , wherein: the step of generating the redundant address includes changing the way counter outputs are mapped as compared to the step of generating the address.
Claim 13
Dependent Claim
40 words
The method for performing a refresh test of claim 10 , wherein: changing the way counter outputs are mapped includes switching the order of counter outputs with a selector when one of the plurality of redundant word lines is activated.
Claim 14
Dependent Claim
25 words
The method for performing a refresh test of claim 10 , wherein: changing the way counter outputs are mapped includes generating a redundancy test signal.
Claim 15
Dependent Claim
20 words
The method for performing a refresh test of claim 7 , wherein: the refresh test is performed before programming redundancy.
Claim 16
Dependent Claim
113 words
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cell plates; each memory cell plate includes a plurality of normal word lines and a plurality of redundant word lines wherein each of the plurality of redundant word lines are programmable to replace a defective one of the plurality of normal word lines; a test circuit that generates redundant word line selection signals so that the plurality of redundant word lines are sequentially selected in each plate without a repeat selection of the same one of the plurality of redundant word lines until all of the plurality of redundant word lines in the plurality of plates have been selected.
Claim 17
Dependent Claim
113 words
A semiconductor memory device, comprising: a memory cell array including a plurality of memory cell plates; each memory cell plate includes a plurality of normal word lines and a plurality of redundant word lines wherein each of the plurality of redundant word lines are programmable to replace a defective one of the plurality of normal word lines; a test circuit that generates redundant word line selection signals so that the plurality of redundant word lines are sequentially selected in each plate without a repeat selection of the same one of the plurality of redundant word lines until all of the plurality of redundant word lines in the plurality of plates have been selected.
Claim 18
Dependent Claim
79 words
The semiconductor memory device of claim 14 , wherein: the plurality of plates includes a first plate and a second plate; the test circuit is responsive to an externally applied selection command to generate the redundant word line selection signals; and when a last one of the plurality of the redundant word lines in the first plate have been selected, one of the plurality of redundant word lines in the second plate is selected on the subsequent selection command.
Claim 19
Dependent Claim
36 words
The semiconductor memory device of claim 15 , wherein: the selection command is a CAS before RAS command received synchronously with an external clock signal; and the semiconductor memory device is a dynamic random access memory.
Claim 20
Dependent Claim
62 words
The semiconductor memory device of claim 14 , wherein: the test circuit includes a counter for generating an address by executing a counting operation every time a selection command is received when normal word lines are selected and a redundancy counter for generating a redundant address by executing counting every time the selection command is received when redundant word lines are selected.
Claim 21
Dependent Claim
48 words
The semiconductor memory device of claim 14 , wherein: the test circuit includes a counter incrementing an address when a selection command is received and an address buffer rearranging the order of the address depending on whether a redundant word line or a normal word line is selected.
Claim 22
Dependent Claim
29 words
The semiconductor memory device of claim 14 , wherein: the address buffer includes a selector for switching the order of the address when a redundant test signal is activated.
Claim 23
Dependent Claim
30 words
The semiconductor memory device of claim 14 , wherein: the test circuit is coupled to receive a redundant test signal being activated when a redundant refresh test command is received.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-07-07 | 2007-01-06 | 2007-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-07-07 | 2011-01-06 | 2011-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-07-07 | 2015-01-06 | 2015-07-08 | $7700.00 | Window Closed / Lapsed |