Voltage stress test circuit for a DRAM

Claim 2

A semiconductor memory device comprising: a DRAM circuit; a voltage stress test mode signal generating circuit for generating a voltage stress test mode signal on the basis of a predetermined signal input through some of external terminals used in a normal operation of said DRAM circuit; and a control circuit for receiving the test mode signal from said voltage stress test mode signal generating circuit, and performing control such that a plurality of bits of an output signal from a refresh address counter of said DRAM circuit are fixed at the same level, and bits other than the plurality of bits are subjected to a normal count operation.

Claim 3

A semiconductor memory device comprising: a DRAM circuit; a voltage stress test mode signal generating circuit for generating a voltage stress test mode signal on the basis of a predetermined signal input through some of external terminals used in a normal operation of said DRAM circuit; and a control circuit for receiving the test mode signal from said voltage stress test mode signal generating circuit, and performing control such that upper bits, of an output signal from a refresh address counter of said DRAM circuit, which are more significant than a specific bit are fixed at the same level, and lower bits which are less significant than the specific bit are subjected to a normal count operation.

Claim 4

A semiconductor memory device comprising: a DRAM circuit; a voltage stress test mode signal generating circuit for generating a voltage stress test mode signal on the basis of a predetermined signal input through some of external terminals used in a normal operation of said DRAM circuit; and a control circuit for receiving the test mode signal from said voltage stress test mode signal generating circuit, and performing control such that upper bits, of an output signal from a refresh address counter of said DRAM circuit, which are more significant than a specific bit are fixed at the same level, and lower bits which are less significant than the specific bit are subjected to a normal count operation.

Claim 5

A device according to claim 2, wherein said DRAM circuit comprises: a memory cell array having a plurality of dynamic memory cells arranged in the form of a matrix; word lines, each connected to said memory cells in the same row of said memory cell array; bit lines, each connected to said memory cells in the same column of said memory cell array; a bit line precharging circuit connected to said bit lines and ON/OFF-controlled by a bit line equalizing signal to precharge said bit lines to a bit line precharging potential; external terminals to which a supply voltage, an address signal, and various control signals are externally input; an address buffer circuit for amplifying an external address signal input through some of said external terminals; a refresh address counter for generating a refresh address signal for a refresh operation of said memory cells; an address switching circuit for selecting either an output signal from said refresh address counter or a row address signal output from said address buffer circuit; a row decoder circuit having a word line selecting function for selecting an arbitrary row in accordance with an internal row address signal output from said address switching circuit; a word line driving circuit, having at least one word line driving MOS transistor connected between a word line driving voltage source and said word lines, for driving said word lines in accordance with an output signal from said row decoder circuit; and a sense amplifier circuit for detecting information read out from said memory cells to said bit lines.

Claim 6

A device according to claim 3, wherein said DRAM circuit includes spare word lines and a spare row decoder/word line driving circuit for a fail-safe operation, and said control circuit further performs control to selectively drive said spare word lines at the same duty ratio as that for normal word lines in a voltage stress test.

Claim 7

A device according to claim 4, wherein said control circuit further performs control to limit a capacity of a driving transistor for said sense amplifier circuit.

Claim 8

A device according to claim 5, wherein said DRAM circuit includes a bit line transfer gate inserted between an input node of said sense amplifier circuit and said bit lines and ON/OFF-controlled by a control signal, and said control circuit further controls said bit line transfer gate in an ON state in a voltage stress test.

Claim 9

A device according to claim 3, wherein said word line driving voltage source is an external power supply for a semiconductor chip, and also serves as a booster circuit for generating a word line driving voltage by boosting a supply voltage, applied from the outside of said semiconductor chip, on said chip, and applying the word line driving voltage as power to said word line driving circuit.

Claim 10

A device according to claim 7, wherein said control circuit further performs control to connect an output node of said booster circuit to an external power supply terminal in a voltage stress test.

Claim 11

A device according to claim 3, wherein said DRAM circuit further includes a supply voltage decreasing circuit for decreasing a supply voltage, applied from the outside of a semiconductor chip, on said chip, and applying the decreased voltage as power to a memory cell peripheral circuit, and said control circuit further performs control to connect an output node of said supply voltage decreasing circuit to an external power supply terminal.

Claim 12

A device according to claim 3, wherein each of said dynamic memory cells includes a transfer gate constituted by an n-channel MOS transistor, and said driving MOS transistor for said word line driving circuit is a p-channel MOS transistor.

Claim 13

A semiconductor memory device comprising said DRAM circuit including: a memory cell array having a plurality of dynamic memory cells arranged in the form of a matrix; word lines, each connected to said memory cells in the same row of said memory cell array; bit lines, each connected to said memory cells in the same column of said memory cell array: a bit line precharging circuit connected to said bit lines and ON/OFF-controlled by a bit line equalizing signal to precharge said bit lines to a bit line precharging potential; external terminals to which a supply voltage, an address signal, and various control signals are externally input; an address buffer circuit for amplifying an external address signal input through some of said external terminals; a refresh address counter the generating a refresh address signal for a refresh operation of said memory cells; an address switching circuit for selecting either an output signal from said refresh address counter or a row address signal output from said address buffer circuit; a row decoder circuit having a word line selecting function for selecting an arbitrary row in accordance with an internal row address signal output from said address switching circuit; a word line driving circuit, having at least one word line driving MOS transistor connected between a word line driving voltage source and said word lines, for driving said word lines in accordance with an output signal from said row decoder circuit; a sense amplifier circuit for detecting information read out from said memory cells to said bit lines; a bit line transfer gate inserted between an input node of said sense amplifier circuit and said bit lines and ON/OFF-controlled by a control signal; a voltage stress test mode signal generating circuit for generating a voltage stress test mode signal on the basis of a predetermined signal input through some of external terminals used in a normal operation of said DRAM circuit; and a control circuit for receiving the test mode signal from said voltage stress test mode signal generating circuit, and performing control such that all bits of an output signal from a refresh address counter of said DRAM circuit are fixed at the same level so as to cause a word line driving circuit of said DRAM circuit to simultaneously drive all word lines.

Claim 14

A semiconductor memory device comprising said DRAM circuit including: a memory cell array having a plurality of dynamic memory cells arranged in the form of a matrix; word lines, each connected to said memory cells in the same row of said memory cell array; bit lines, each connected to said memory cells in the same column of said memory cell array: a bit line precharging circuit connected to said bit lines and ON/OFF-controlled by a bit line equalizing signal to precharge said bit lines to a bit line precharging potential; external terminals to which a supply voltage, an address signal, and various control signals are externally input; an address buffer circuit for amplifying an external address signal input through some of said external terminals; a refresh address counter the generating a refresh address signal for a refresh operation of said memory cells; an address switching circuit for selecting either an output signal from said refresh address counter or a row address signal output from said address buffer circuit; a row decoder circuit having a word line selecting function for selecting an arbitrary row in accordance with an internal row address signal output from said address switching circuit; a word line driving circuit, having at least one word line driving MOS transistor connected between a word line driving voltage source and said word lines, for driving said word lines in accordance with an output signal from said row decoder circuit; a sense amplifier circuit for detecting information read out from said memory cells to said bit lines; a bit line transfer gate inserted between an input node of said sense amplifier circuit and said bit lines and ON/OFF-controlled by a control signal; a voltage stress test mode signal generating circuit for generating a voltage stress test mode signal on the basis of a predetermined signal input through some of external terminals used in a normal operation of said DRAM circuit; and a control circuit for receiving the test mode signal from said voltage stress test mode signal generating circuit, and performing control such that all bits of an output signal from a refresh address counter of said DRAM circuit are fixed at the same level so as to cause a word line driving circuit of said DRAM circuit to simultaneously drive all word lines.

Claim 15

A device according to claim 11, wherein said DRAM circuit includes spare word lines and a spare row decoder/word line driving circuit for a fail-safe operation, and said control circuit further performs control to selectively drive said spare word lines in a voltage stress test.

Claim 16

A device according to claim 12, wherein said control circuit further performs control in a voltage stress test such that said bit line transfer gate and said bit line equalizing circuit are set in an ON state, and the bit line precharging potential is set at a low level so as to inhibit operations of said sense amplifier circuit and a circuit on an output side thereof.

Claim 17

A device according to claim 11, wherein said word line driving voltage source is an external power supply for a semiconductor chip, and also serves as a booster circuit for generating a word line driving voltage by boosting a supply voltage, applied from the outside of said semiconductor chip, on said chip, and applying the word line driving voltage as power to said word line driving circuit.

Claim 18

A device according to claim 14, wherein said control circuit further performs control to connect an output node of said booster circuit to an external power supply terminal in a voltage stress test.

Claim 19

A device according to claim 11, wherein said DRAM circuit further includes a supply voltage decreasing circuit for decreasing a supply voltage, applied from the outside of a semiconductor chip, on said chip, and applying the decreased voltage as power to a memory cell peripheral circuit, and said control circuit further performs control to connect an output node of said supply voltage decreasing circuit to an external power supply terminal.

Claim 20

A device according to claim 11, wherein each of said dynamic memory cells includes a transfer gate constituted by an n-channel MOS transistor, and said driving MOS transistor for said word line driving circuit is a p-channel MOS transistor.