Patent US6587912B2 successfully refreshed from Google Patents.
US6587912B2
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Method and apparatus for implementing multiple memory buses on a memory module
Assignee: Intel Corp
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Filing: 1998-09-30
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Granted: 2003-07-01
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Expires: 2018-09-30
Abstract
Abstract A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.
Inventors
- 👤 Michael W. Leddige
- 👤 Bryce D. Horine
- 👤 Randy Bonella
- 👤 Peter D. MacWilliams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:32
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4247; G06F13/4256
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
104 words
A memory module, comprising: a first memory bus to transmit memory signals on and off the memory module; a second memory bus to transmit the memory signals to a plurality of memory devices on the memory module; and a memory repeater coupled to the first and second memory buses, the memory repeater to determine whether the memory signals received via the first memory bus are to be transmitted to the plurality of memory devices via the second memory bus, and the memory repeater to determine whether to direct the memory signals off the memory module to another memory module via the first memory bus.
Claim 2
Dependent Claim
104 words
A memory module, comprising: a first memory bus to transmit memory signals on and off the memory module; a second memory bus to transmit the memory signals to a plurality of memory devices on the memory module; and a memory repeater coupled to the first and second memory buses, the memory repeater to determine whether the memory signals received via the first memory bus are to be transmitted to the plurality of memory devices via the second memory bus, and the memory repeater to determine whether to direct the memory signals off the memory module to another memory module via the first memory bus.
Claim 3
Dependent Claim
38 words
The memory module of claim 1 , further comprising a third memory bus coupled to the memory repeater, wherein the third memory bus is to transmit memory signals to a plurality of memory devices on the memory module.
Claim 4
Dependent Claim
32 words
The memory module of claim 1 , wherein the first memory bus is routed from tire memory repeater to an electrical connector that routes the first memory bus off the memory module.
Claim 5
Dependent Claim
88 words
The memory module of claim 1 , wherein the memory signals include address information, and the memory repeater includes control logic with an addressing unit, the addressing unit to read the address information and determine whether the memory signals should go to the plurality of memory devices on the memory module, and the control logic to direct the memory signals to either the first bus, if the memory signals should go to the plurality of memory devices, or the second bus to be routed off the memory module.
Claim 6
Dependent Claim
59 words
The memory module of claim 4 , wherein the address information includes a memory address with a first portion and a second portion, the addressing unit to read the first portion to identify a memory device to be accessed, and the addressing unit to read the second portion to identify a memory bus which the memory device is on.
Claim 7
Dependent Claim
64 words
The memory module of claim 5 , wherein the memory signals include control information, and the control logic is to direct the control information to a control interface circuit to route the control information to either the second memory bus, if the memory device is on the memory module, or to route the control information off the memory module via the first memory bus.
Claim 8
Dependent Claim
64 words
The memory module of claim 5 , wherein the memory signals include data signals, and the control logic is to direct the data signals to a data I/O circuitry to route the data signals to either the second memory bus, if the memory device is on the memory module, or to route the data signals off the memory module via the first memory bus.
Claim 9
Dependent Claim
45 words
The memory module of claim 1 , wherein the memory signals from the memory controller have address information and control information, and wherein the memory repeater includes request handling logic to interface with the first memory bus and receives the control information and address information.
Claim 10
Dependent Claim
43 words
The memory module of claim 8 , wherein the address and control information are multiplexed and the request handling logic includes deserializing logic to separate the multiplexed control and address information, and to provide the separated control and address information to control logic.
Claim 11
Dependent Claim
21 words
The memory module of claim 8 , wherein the request handling logic includes serializing logic to serialize control and address information.
Claim 12
Dependent Claim
48 words
The memory module of claim 1 , wherein the memory signals from the memory controller contain data signals, and wherein the memory repeater includes data handling logic to receive the data signals and to reformat the data signals into a format appropriate for the plurality of memory devices.
Claim 13
Dependent Claim
47 words
The memory module of claim 11 , further including any one of a write buffer, a read buffer, and data input/output (I/O) circuitry, the write buffer and read buffer connected to the data I/O circuitry, and the data I/O circuitry connected to the plurality of memory devices.
Claim 14
Dependent Claim
123 words
A computer system, comprising: a bus; a processor coupled to the bus; a memory controller coupled to the bus; a first memory bus to transmit memory signals from the memory controller; and a memory system, that includes a first memory module coupled to the memory controller via the first memory bus, the first memory module having a second memory bus connected with the first memory bus via a memory repeater, wherein the memory repeater is to determine whether the memory signals received via the first memory bus are to be transmitted to the first memory module via the second memory bus, and the memory repeater to determine whether to direct the memory signal to a second memory module via the first memory bus.
Claim 15
Dependent Claim
123 words
A computer system, comprising: a bus; a processor coupled to the bus; a memory controller coupled to the bus; a first memory bus to transmit memory signals from the memory controller; and a memory system, that includes a first memory module coupled to the memory controller via the first memory bus, the first memory module having a second memory bus connected with the first memory bus via a memory repeater, wherein the memory repeater is to determine whether the memory signals received via the first memory bus are to be transmitted to the first memory module via the second memory bus, and the memory repeater to determine whether to direct the memory signal to a second memory module via the first memory bus.
Claim 16
Dependent Claim
23 words
The computer system of claim 13 , further comprising a third memory bus coupled with the first memory bus via the memory repeater.
Claim 17
Dependent Claim
25 words
The computer system of claim 14 , further comprising a plurality of memory devices on the first memory module coupled to the third memory bus.
Claim 18
Dependent Claim
25 words
The computer system of claim 13 , further comprising a plurality of memory devices on the first memory module coupled to the second memory bus.
Claim 19
Dependent Claim
32 words
The computer system of claim 13 , wherein the first memory bus is routed from the memory repeater to an electrical connector that routes the first memory bus off the memory module.
Claim 20
Dependent Claim
19 words
The computer system of claim 17 , further comprising a second memory module coupled to the first memory bus.
Claim 21
Dependent Claim
31 words
The computer system of claim 18 , wherein the second memory module further comprises a third memory bus connected in series with the first memory bus via a second memory repeater.
Claim 22
Dependent Claim
25 words
The computer system of claim 19 , further comprising a plurality of memory devices on the second memory module coupled to the third memory bus.
Claim 23
Dependent Claim
25 words
The computer system of claim 18 , further comprising a plurality of memory devices on the second memory module coupled to the first memory bus.
Claim 24
Dependent Claim
89 words
The memory module of claim 13 , wherein the memory signals include address information, and the memory repeater includes control logic with an addressing unit, the addressing unit to read the address information and determine whether the memory signals should go to the plurality of memory devices on the first memory module, and the control logic to direct the memory signals to either the first bus, if the memory signals should go to the plurality of memory devices, or the second bus to be routed off the memory module.
Claim 25
Dependent Claim
58 words
The computer system of claim 22 , wherein the address information includes memory address with a first portion and a second portion, the addressing unit to read the first portion to identify a memory device to be accessed, and the addressing unit to read the second portion to identify a memory bus which the memory device is on.
Claim 26
Dependent Claim
64 words
The computer system of claim 23 , wherein the memory signals include control information, and the control logic is to direct the control information to a control interface circuit to route the control information to either the second memory bus, if the memory device is on the memory module, or to route the control information off the memory module via the first memory bus.
Claim 27
Dependent Claim
64 words
The computer system of claim 23 , wherein the memory signals include data signals, and the control logic is to direct the data signals to a data I/O circuitry to route the data signals to either the second memory bus, if the memory device is on the memory module, or to route the data signals off the memory module via the first memory bus.
Claim 28
Dependent Claim
45 words
The computer system of claim 13 , wherein the memory signals from the memory controller have address information and control information, and wherein the memory repeater includes request handling logic to interface with the first memory bus and receives the control information and address information.
Claim 29
Dependent Claim
43 words
The computer system of claim 26 , wherein the address and control information are multiplexed and the request handling logic includes deserializing logic to separate the multiplexed control and address information, and to provide the separated control and address information to control logic.
Claim 30
Dependent Claim
21 words
The computer system of claim 27 , wherein the request handling logic includes serializing logic to serialize control and address information.
Claim 31
Dependent Claim
48 words
The computer system of claim 13 , wherein the memory signals from the memory controller contain data signals, and wherein the memory repeater includes data handling logic to receive the data signals and to reformat the data signals into a format appropriate for the plurality of memory devices.
Claim 32
Dependent Claim
47 words
The computer system of claim 29 , further including any one of a write buffer, a read buffer, and data input/output (I/O) circuitry, the write buffer and read buffer connected to the data I/O circuitry, and the data I/O circuitry connected to the plurality of memory devices.
Claim 33
Dependent Claim
120 words
A memory module, comprising: a first memory bus to transmit memory signals on and off the memory module; a second memory bus to transmit the memory signals to a first plurality of memory devices; a third memory bus, connected in parallel with the second memory bus, to transmit the memory signals to a second plurality of memory devices on the memory module; and a memory repeater coupled to the first, second, and third memory buses to determine whether the memory signals received via the first memory bus are to be transmitted to the first or second plurality of memory devices via the second or third memory buses, or to be routed off the memory module via the first memory bus.
Claim 34
Dependent Claim
120 words
A memory module, comprising: a first memory bus to transmit memory signals on and off the memory module; a second memory bus to transmit the memory signals to a first plurality of memory devices; a third memory bus, connected in parallel with the second memory bus, to transmit the memory signals to a second plurality of memory devices on the memory module; and a memory repeater coupled to the first, second, and third memory buses to determine whether the memory signals received via the first memory bus are to be transmitted to the first or second plurality of memory devices via the second or third memory buses, or to be routed off the memory module via the first memory bus.
Claim 35
Dependent Claim
32 words
The memory module of claim 31 , wherein the first memory bus is routed from the memory repeater to an electrical connector that routes the third memory bus off the memory module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-30 | 2006-12-30 | 2007-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-30 | 2010-12-30 | 2011-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-30 | 2014-12-30 | 2015-07-01 | $7700.00 | Window Closed / Lapsed |