US6586989B2
Expired / Lapsed
US
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Nonlinear digital differential amplifier offset calibration
Assignee: Samsung Electronics Co Ltd
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Filing: 2001-11-06
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Granted: 2003-07-01
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Expires: 2021-11-06
Abstract
Abstract Circuits and methods for calibrating offset error in a differential amplifier in an efficient and reliable way are described. A final calibrated state for the differential amplifier is obtained in accordance with a nonlinear search that requires significantly fewer test stages to complete than linear search methods. As a result, longer test periods may be used with the invention without adversely affecting the overall length of the calibration process. Because circuit conditions near the calibration point cause internal test signals to switch more slowly from one state to another, lengthening the test period time may allow more time for the internal test signals to reach their final values and, thereby, improve calibration accuracy.
Inventors
- 👤 Frederick A. Perner
- 👤 Kenneth K. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:55
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/45632; H03F3/45744
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
173 words
A circuit for calibrating offset error in a differential amplifier, comprising: a memory circuit operable to store a set of programming values selected from a range of multiple possible sets of programming values; an output circuit coupled to the memory circuit and operable to place the differential amplifier in a selected calibrated state by applying to the differential amplifier an output calibration signal generated based upon the set of programming values stored in the memory circuit; and a control circuit coupled to the memory circuit and operable to program the memory circuit with a final set of programming values by progressively narrowing the range of possible programming value sets until the final set of programming values is obtained, the range of possible programming value sets being progressively narrowed in test stages in accordance with a nonlinear search, wherein at each test stage a set of programming values is selected based upon a sensed differential amplifier signal generated in response to a test signal applied to the differential amplifier in a selected calibrated state.
Claim 2
Dependent Claim
173 words
A circuit for calibrating offset error in a differential amplifier, comprising: a memory circuit operable to store a set of programming values selected from a range of multiple possible sets of programming values; an output circuit coupled to the memory circuit and operable to place the differential amplifier in a selected calibrated state by applying to the differential amplifier an output calibration signal generated based upon the set of programming values stored in the memory circuit; and a control circuit coupled to the memory circuit and operable to program the memory circuit with a final set of programming values by progressively narrowing the range of possible programming value sets until the final set of programming values is obtained, the range of possible programming value sets being progressively narrowed in test stages in accordance with a nonlinear search, wherein at each test stage a set of programming values is selected based upon a sensed differential amplifier signal generated in response to a test signal applied to the differential amplifier in a selected calibrated state.
Claim 3
Dependent Claim
17 words
The calibration circuit of claim 1 , wherein the memory circuit comprises a set of calibration registers.
Claim 4
Dependent Claim
20 words
The calibration circuit of claim 2 , wherein each calibration register is gated by a set of global select signals.
Claim 5
Dependent Claim
15 words
The calibration circuit of claim 2 , wherein each calibration register is settable and re-settable.
Claim 6
Dependent Claim
21 words
The calibration circuit of claim 1 , wherein the output circuit comprises a coarse calibration circuit and a fine calibration circuit.
Claim 7
Dependent Claim
18 words
The calibration circuit of claim 5 , wherein the coarse calibration circuit comprises a programmable voltage divider circuit.
Claim 8
Dependent Claim
34 words
The calibration circuit of claim 5 , wherein the coarse calibration circuit is operable to adjust back gate bias voltages applied to one or more transistors in an input stage of the differential amplifier.
Claim 9
Dependent Claim
17 words
The calibration circuit of claim 5 , wherein the fine calibration circuit comprises a programmable impedance circuit.
Claim 10
Dependent Claim
31 words
The calibration circuit of claim 5 , wherein the fine calibration circuit is operable to adjust impedance values of one or more transistors in an input stage of the differential amplifier.
Claim 11
Dependent Claim
44 words
The calibration circuit of claim 1 , wherein the control circuit is operable to generate a test programming value at a beginning portion of a given test stage and to select a final programming value at an end portion of the given test stage.
Claim 12
Dependent Claim
34 words
The calibration circuit of claim 10 , wherein a selected delay period separates periods during a given test stage when the test programming value is generated and when the final programming value is selected.
Claim 13
Dependent Claim
26 words
The calibration circuit of claim 1 , wherein the control circuit progressively narrows the range of possible programming value sets in accordance with a binary search.
Claim 14
Dependent Claim
34 words
The calibration circuit of claim 12 , wherein the control circuit progressively narrows the range of possible programming value sets by selecting one value of the final programming value set during each test stage.
Claim 15
Dependent Claim
28 words
The calibration circuit of claim 13 , wherein the values of the final programming value set are selected in order from most significant bit to least significant bit.
Claim 16
Independent Claim
150 words
A method of calibrating offset error in a differential amplifier, comprising: storing in a memory circuit a set of programming values selected from a range of multiple possible sets of programming values; placing the differential amplifier in a selected calibrated state by applying to the differential amplifier an output calibration signal generated based upon the set of programming values stored in the memory circuit; and programming the memory circuit with a final set of programming values by progressively narrowing the range of possible programming value sets until the final set of programming values is obtained, the range of possible programming value sets being progressively narrowed in test stages in accordance with a nonlinear search, wherein at each test stage a set of programming values is selected based upon a sensed differential amplifier signal generated in response to a test signal applied to the differential amplifier in a selected calibrated state.
Claim 17
Independent Claim
150 words
A method of calibrating offset error in a differential amplifier, comprising: storing in a memory circuit a set of programming values selected from a range of multiple possible sets of programming values; placing the differential amplifier in a selected calibrated state by applying to the differential amplifier an output calibration signal generated based upon the set of programming values stored in the memory circuit; and programming the memory circuit with a final set of programming values by progressively narrowing the range of possible programming value sets until the final set of programming values is obtained, the range of possible programming value sets being progressively narrowed in test stages in accordance with a nonlinear search, wherein at each test stage a set of programming values is selected based upon a sensed differential amplifier signal generated in response to a test signal applied to the differential amplifier in a selected calibrated state.
Claim 18
Dependent Claim
39 words
The calibration method of claim 15 , further comprising generating a test programming value at a beginning portion of a given test stage and to selecting a final programming value at an end portion of the given test stage.
Claim 19
Dependent Claim
33 words
The calibration method of claim 16 , wherein a selected delay period separates when the test programming value is generated and when the final programming value is selected during a given test stage.
Claim 20
Dependent Claim
24 words
The calibration method of claim 15 , wherein the range of possible programming value sets is progressively narrowed in accordance with a binary search.
Claim 21
Dependent Claim
32 words
The calibration method of claim 18 , wherein the range of possible programming value sets is progressively narrowed by selecting one value of the final programming value set during each test stage.
Claim 22
Dependent Claim
28 words
The calibration method of claim 19 , wherein the values of the final programming value set are selected in order from most significant bit to least significant bit.
References Cited (Backward Citations)
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