Efficient internal address encoding scheme for an integrated circuit which facilitates multiple addressing modes

Abstract

Abstract An address line arrangement which uses weighted sets of mutually independent rather than binary address lines to enable the accessing of any number of targeted elements at one time. The elements in a device are divided into groups of elements. For a numerical example, assume four elements per group and eight groups per device. One set of four address lines is wired to access one or all groups in one half of the device and a second set of four lines will access one or all groups in the other half of the device. A third set of four address lines is wired to all elements and will access one, two or all elements in each group at a time. Each element is wired to one line in the first or second group and one line in the second or third group. Since all address lines can be individually turned on, one or more elements can be accessed at one time.

Inventors

• 👤 David R. Duval

Bibliographic Details