Patent US6577348B1 successfully refreshed from Google Patents.
US6577348B1
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Apparatus and method for digitizing an analog video signal
Assignee: LG Electronics Inc
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Filing: 2000-03-27
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Granted: 2003-06-10
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Expires: 2020-03-27
Abstract
Abstract A video processing method and apparatus for displaying a signal input in an analog form in a digital TV is disclosed. The present invention eliminates an interference between signals by unifying a flow of analog video signals having different formats, and several signal formats are processed without change through a basic construction of the hardware. Also, the efficiency is increased by utilizing an ADC, a clock and a clamp pulse generation in common for signals based on different formats. Furthermore, a stable interface operation is executed by reconstructing a horizontal synchronization with a constant width in a clock base, and performing a combination and a separation of digital signals on the basis of such construction.
Inventors
- 👤 Dong Ho Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:42
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/46; H04N7/00; H04N7/12; H04N5/14; H04N7/01; H04N21/00; H04N21/40; H04N21/41; H04N21/426; H04N5/445; H04N5/45
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
121 words
A video processing apparatus of a digital TV comprising: a selector which receives at least one analog video signal, synchronizes the received analog video signals into a predetermined format, selects and outputs an analog video signal of said predetermined format; a clock generator which generates a clock locked with the analog video signal of said predetermined format; an ADC which receives and digitalizes the analog video signal of said predetermined format, in synchronization to the clock, and outputs a digitalized video signal; a display format converter which converts the digitalized video signal to match a display format; and a controller which controls the selection of an analog video signal in the selector and controls said clock generation in the clock generator.
Claim 2
Dependent Claim
121 words
A video processing apparatus of a digital TV comprising: a selector which receives at least one analog video signal, synchronizes the received analog video signals into a predetermined format, selects and outputs an analog video signal of said predetermined format; a clock generator which generates a clock locked with the analog video signal of said predetermined format; an ADC which receives and digitalizes the analog video signal of said predetermined format, in synchronization to the clock, and outputs a digitalized video signal; a display format converter which converts the digitalized video signal to match a display format; and a controller which controls the selection of an analog video signal in the selector and controls said clock generation in the clock generator.
Claim 3
Dependent Claim
14 words
An apparatus of claim 1 , wherein the predetermined format is a Y,Cb,Cr format.
Claim 4
Dependent Claim
31 words
An apparatus of claim 1 , wherein said selector converts a polarity of a synchronization signal into a polarity of an NTSC if the received analog video signal is a VGA.
Claim 5
Dependent Claim
54 words
An apparatus of claim 1 , further comprising a clamp pulse generator which receives a horizontal synchronization signal through said selector, generates a clamp pulse at a section following a generation of said horizontal synchronization signal, but prior to an active data; said clamp pulse generator outputting the generated clamp pulse to the ADC.
Claim 6
Dependent Claim
44 words
An apparatus of claim 4 , wherein the clamp pulse generator is implemented by a retriggerable single shot, wherein a trigger is provided by said horizontal synchronization signal and a clamp pulse with an adequate width is generated by controlling an RC time constant.
Claim 7
Dependent Claim
43 words
An apparatus of claim 1 , wherein said controller reads a register value corresponding to a signal source in a predetermined table to control said clock generation, wherein said register value is read according to the analog video signal selected by the selector.
Claim 8
Dependent Claim
33 words
An apparatus of claim 1 , further comprising a field detector which obtains field information when the input analog video signal is NTSC, and outputs the field information to the display format converter.
Claim 9
Dependent Claim
108 words
An apparatus of claim 7 , wherein said field detector comprises: a normal field detector which detects the field information from a relation between a horizontal and a vertical synchronization output from said selector; an abnormal field detector which forcefully generates the field information from the vertical synchronization output from said selector; a multiplexer which selects a field information from either the normal field detector or the abnormal field detector according to a selection signal, and outputs the selected field information to said display format converter; and a selection controller which outputs said selection signal based upon whether said field information from the normal field detector is stable.
Claim 10
Dependent Claim
77 words
An apparatus of claim 8 , wherein said normal field detector detects the field information by delaying the starting point of the horizontal synchronization starting point using a first signal one shot of a low time constant in a synchronization phase variance to trigger the leading edge of the horizontal synchronization, and by extending the low edge of the horizontal synchronization using a second single one shot to trigger the trailing edge of a first signal output.
Claim 11
Dependent Claim
98 words
An apparatus of claim 1 , further comprising: a multiplexer which multiplexes digitalized Cb and Cr color signals from the ADC in response to a selection signal; a horizontal synchronization regenerator which generates a pulse based upon said clock at a point in time immediately after a leading edge of a horizontal synchronization from said selector, logically combines the generated pulse with n-clock delayed pulses, and generates a reconstructed horizontal synchronization; and a selection signal generator which generates the selection signal according to said clock and the reconstructed horizontal synchronization, and outputs the selection signal to the multiplexer.
Claim 12
Independent Claim
103 words
A method of processing video in a digital TV comprising: (a1) receiving at least one analog video signal, synchronizing the received analog video signals into a predetermined format, selecting and outputting an analog video signal of said predetermined format; (b1) generating a clock locked with the analog video signal of said predetermined format; (c1) digitalizing the analog video signal of said predetermined format, in synchronization to the clock, and outputting a digitalized video signal; (d1) converting the digitalized video signal to match a display format; and (e1) controlling the selection of an analog video signal in (a1) and controlling said clock generation (b1).
Claim 13
Independent Claim
103 words
A method of processing video in a digital TV comprising: (a1) receiving at least one analog video signal, synchronizing the received analog video signals into a predetermined format, selecting and outputting an analog video signal of said predetermined format; (b1) generating a clock locked with the analog video signal of said predetermined format; (c1) digitalizing the analog video signal of said predetermined format, in synchronization to the clock, and outputting a digitalized video signal; (d1) converting the digitalized video signal to match a display format; and (e1) controlling the selection of an analog video signal in (a1) and controlling said clock generation (b1).
Claim 14
Dependent Claim
14 words
A method of claim 11 , wherein the predetermined format is a Y,CB,CR format.
Claim 15
Dependent Claim
31 words
A method of claim 11 , wherein in (a1) converting a polarity of a synchronization signal into a polarity of an NTSC if the received analog video signal is a VGA.
Claim 16
Dependent Claim
40 words
A method of claim 11 , further comprising generating a clamp pulse at a section following a generation of a horizontal synchronization signal, but prior to an active data, and outputting the generated clamp pulse to be used in (c1).
Claim 17
Dependent Claim
37 words
A method of claim 11 , wherein in (e1), reading a register value corresponding to a signal source in a predetermined table to control said clock generation, according to the analog video signal selected by the selector.
Claim 18
Dependent Claim
29 words
A method of claim 11 , further comprising obtaining field information when the input analog video signal is NTSC, and outputting the field information to the display format converter.
Claim 19
Dependent Claim
82 words
A method of claim 16 , wherein obtaining the field information comprises: (a2) detecting the field information from a relation between a horizontal and a vertical synchronization; (b2) forcefully generating the field information from the vertical synchronization; (c2) selecting a field information from either (a2) or (b2) according to a selection signal, and outputting the selected field information to be used in (d1); and (d2) generating said selection signal based upon whether said field information from the normal field detector is stable.
Claim 20
Dependent Claim
75 words
A method of claim 17 , wherein in (a2), detecting the field information by delaying the starting point of the horizontal synchronization starting point using a first signal one shot of a low time constant in a synchronization phase variance to trigger the leading edge of the horizontal synchronization, and by extending the low edge of the horizontal synchronization using a second single one shot to trigger the trailing edge of a first signal output.
Claim 21
Dependent Claim
76 words
A method of claim 11 , further comprising: multiplexing Cb and Cr color signals digitalized in (c1) in response to a selection signal; generating a pulse based upon said clock at a point in time immediately after a leading edge of a horizontal synchronization from said selector, logically combining the generated pulse with n-clock delayed pulses, and generating a reconstructed horizontal synchronization; and generating the selection signal according to said clock and the reconstructed horizontal synchronization.
References Cited (Backward Citations)
US5784113A
Cited
US6211918B1
Cited
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| 3.5 Years (Year 4) | 2006-06-09 | 2006-12-09 | 2007-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-09 | 2010-12-09 | 2011-06-10 | $3760.00 | Window Closed / Lapsed |
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