Initializing a memory controller by executing software in second memory to wakeup a system

Claim 2

In a system comprising a processor, a first memory, a first memory controller, and a second memory, a method for transitioning between an awake state and a sleep state comprising: detecting a trigger to transition from the sleep state to the awake state; initializing the first memory controller in response to the detecting, the initializing comprising executing software in the second memory; and executing software in the first memory after the initializing.

Claim 3

The method of claim 1 further comprising: preparing, under control of software stored in the first memory, for a transition from the awake state to the sleep state; and transitioning to the sleep state.

Claim 4

The method of claim 2 wherein the software stored in the first memory comprises operating system software.

Claim 5

The method of claim 2 wherein the first memory comprises RDRAM.

Claim 6

The method of claim 4 wherein the first memory controller resides in the same chip as the processor.

Claim 7

The method of claim 5 wherein the software in the second memory comprises BIOS software.

Claim 8

The method of claim 5 wherein the software in the second memory comprises software inaccessible by the operating system.

Claim 9

The method of claim 5 wherein the software in the second memory comprises system management mode software.

Claim 10

The method of claim 1 wherein the processor and memory controller have inputs for receiving respective clock signals, the method further comprising preventing the receiving of the respective clock signals prior to the detecting.

Claim 11

The method of claim 2 wherein the preparing comprises: configuring the processor to execute the software stored in the second memory in response to a sleep trigger signal from the operating system; receiving a first sleep trigger signal from the operating system; executing the software stored in the second memory in response to the receiving; reconfiguring the processor to transition to the sleep state in response to a sleep trigger signal; and receiving a second sleep trigger signal.

Claim 12

The method of claim 10 wherein the software stored in the second memory comprises system management mode software, the method further comprising generating a system management interrupt in response to the receiving of the first sleep trigger.

Claim 13

The method of claim 10 wherein the initializing executes the software stored in the second memory at the instruction following the last instruction executed before transitioning to the sleep state.

Claim 14

The method of claim 2 wherein the transitioning transitions the processor into an S 1 state.

Claim 15

The method of claim 2 wherein the transitioning transitions the processor into an S 2 state.

Claim 16

The method of claim 2 wherein the preparing comprises flushing a cache.

Claim 17

The method of claim 2 further comprising resetting the processor prior to the initializing.

Claim 18

In a system comprising a processor, a first memory, a first memory controller, and a second memory, wherein the processor and memory controller have inputs for receiving respective clock signals, and the first memory stores operating system software, a method for transitioning between an awake state and a sleep state comprising: preparing, under control of the operating system software, for a transition from the awake state to the sleep state, the preparing including configuring the address space mapping to point to the second memory following the detecting; preventing the receiving of the respective clock signals; transitioning to the sleep state; detecting a trigger to transition from the sleep state to the awake state; initializing the first memory controller in response to the detecting, the initializing comprising executing BIOS software in the second memory; executing operating system software after the initializing.

Claim 19

In a system comprising a processor, a first memory, a first memory controller, and a second memory, wherein the processor and memory controller have inputs for receiving respective clock signals, and the first memory stores operating system software, a method for transitioning between an awake state and a sleep state comprising: preparing, under control of the operating system software, for a transition from the awake state to the sleep state, the preparing including configuring the address space mapping to point to the second memory following the detecting; preventing the receiving of the respective clock signals; transitioning to the sleep state; detecting a trigger to transition from the sleep state to the awake state; initializing the first memory controller in response to the detecting, the initializing comprising executing BIOS software in the second memory; executing operating system software after the initializing.

Claim 20

The method of claim 17 further comprising: storing a BIOS resume address in the first memory; and transferring control from the BIOS to the operating system following the initializing using the resume address stored in the first memory.

Claim 21

The method of claim 18 further comprising powering down the first memory controller prior to the detecting.

Claim 24

The system of claim 20 wherein: the first memory stores operating system software; the second memory is nonvolatile memory; the second memory stores BIOS software; and the operating system software is configured to control a transition from the awake state to the sleep state.

Claim 25

The system of claim 21 wherein: the operating system stores a BIOS resume address in the first memory prior to a transition from the awake state to the sleep state; and the BIOS software returns control to the operating system using the stored BIOS resume address after the memory controller is initialized.

Claim 26

The system of claim 21 wherein the first memory comprises RDRAM.

Claim 27

The system of claim 21 wherein the second memory comprises RAM.

Claim 28

The system of claim 21 further comprising system management mode software, the system management mode software being inaccessible by the operating system, and wherein the system management mode software initializes the first memory.

Claim 29

The system of claim 20 wherein the processor, first memory, and first memory controller have clock inputs, the system comprising clock disable circuitry preventing the internal clocking of the processor, first memory, and first memory controller.

Claim 30

The system of claim 20 wherein the processor and first memory controller reside within a common chip.

Claim 31

The system of claim 20 further comprising cache residing in the same chip as the processor and first memory controller and wherein the operating system is configured to flush the cache prior to the transition from the awake state to the sleep state.

Claim 32

A portable computer system comprising: a power storage medium; a display; a processor; a processor clock; a first memory; a first memory controller; a second memory; wherein the system includes an awake state and a sleep state; wherein the processor and first memory controller are not clocked in the sleep state; and wherein software in the second memory initializes the first memory controller responsive to a transition from the sleep state to the awake state.

Claim 33

A portable computer system comprising: a power storage medium; a display; a processor; a processor clock; a first memory; a first memory controller; a second memory; wherein the system includes an awake state and a sleep state; wherein the processor and first memory controller are not clocked in the sleep state; and wherein software in the second memory initializes the first memory controller responsive to a transition from the sleep state to the awake state.

Claim 34

The system of claim 29 further comprising circuitry to disable the flow of power internal to the processor, first memory controller, and first memory.