US6571206B1 — Apparatus and method for emulating an I/O instruc…

Claim 1

Independent Claim 180 words

A multi-processor system, comprising: a plurality of processors, each capable of executing an I/O instruction to transfer data or a command between the plurality of processors and an I/O device; I/O and trap hardware for performing an interrupt on the plurality of processors upon receipt of a selected I/O instruction from one of the plurality of processors and to transfer data or a command between the I/O device and said one of the plurality of processors; a first device for determining which of the plurality of processors is an executing processor, where the executing processor is executing the selected I/O instruction, said first device to utilize a save state area for each of the plurality of processors; a second device operating, when only one of the plurality of processors is executing an I/O instruction, to set a LastProcessor indicator designating which of the plurality of processors is the executing processor; and a third device for transferring data or a command between the executing processor indicated in the LastProcessor indicator and the I/O device in response to the selected I/O instruction.

Claim 2

Dependent Claim 180 words

A multi-processor system, comprising: a plurality of processors, each capable of executing an I/O instruction to transfer data or a command between the plurality of processors and an I/O device; I/O and trap hardware for performing an interrupt on the plurality of processors upon receipt of a selected I/O instruction from one of the plurality of processors and to transfer data or a command between the I/O device and said one of the plurality of processors; a first device for determining which of the plurality of processors is an executing processor, where the executing processor is executing the selected I/O instruction, said first device to utilize a save state area for each of the plurality of processors; a second device operating, when only one of the plurality of processors is executing an I/O instruction, to set a LastProcessor indicator designating which of the plurality of processors is the executing processor; and a third device for transferring data or a command between the executing processor indicated in the LastProcessor indicator and the I/O device in response to the selected I/O instruction.

Claim 3

Dependent Claim 49 words

A multi-processor system, as defined in claim 1 , wherein the I/O and trap hardware comprises an emulation block for translating the data or command from one of the I/O device and executing processor to a different format compatible with the other of the I/O device and executing processor.

Claim 4

Dependent Claim 109 words

A multi-processor system, as defined in claim 1 , wherein the first device for determining which of the processors is executing the selected I/O instruction comprises first circuitry for designating for each of the plurality of processors, whether an instruction address count difference between an instruction address for an I/O instruction last performed by a particular processor and a current instruction address for the particular processor is less than or equal to a predetermined number, and using this designation in determining which of the plurality of processors is the executing processor, said instruction address to be held in said save state area for each of said plurality of processors.

Claim 5

Dependent Claim 61 words

A multi-processor system, as defined in claim 3 , wherein the first circuitry includes logic to determine when the instruction address count difference for the particular processor is one, and to delete the designation of the particular processor as the executing processor unless the last I/O instruction for the particular processor designates directly or indirectly a port for the I/O device.

Claim 6

Dependent Claim 15 words

A multi-processor system as defined in claim 3 , wherein the predetermined number is two.

Claim 7

Dependent Claim 54 words

A multi-processor system as defined in claim 1 , wherein each of the plurality of processors includes a first logic to set a first indicator when it is executing an I/O instruction; and wherein the first device comprises a second logic to determine which of the plurality of processors have their first indicators set.

Claim 8

Independent Claim 149 words

A method for controlling I/O in a multi-processor environment, comprising: determining if an I/O instruction requiring an interrupt is being executed by one of a plurality of processors in the multi-processor environment to transfer data or a command between the one of the plurality of processors and an I/O device; performing an interrupt if the I/O instruction is detected; determining which of the plurality of processors in said multi-processor environment is an executing processor by utilizing a save state area of each of the plurality of processors, where the executing processor is executing the I/O instruction; if only one of the plurality of processors is executing the I/O instruction, setting a LastProcessor indicator designating which of the plurality of processors is the executing processor; and transferring data or a command between the executing processor designated in the LastProcessor indicator and the I/O device in response to the I/O instruction.

Claim 9

Independent Claim 149 words

A method for controlling I/O in a multi-processor environment, comprising: determining if an I/O instruction requiring an interrupt is being executed by one of a plurality of processors in the multi-processor environment to transfer data or a command between the one of the plurality of processors and an I/O device; performing an interrupt if the I/O instruction is detected; determining which of the plurality of processors in said multi-processor environment is an executing processor by utilizing a save state area of each of the plurality of processors, where the executing processor is executing the I/O instruction; if only one of the plurality of processors is executing the I/O instruction, setting a LastProcessor indicator designating which of the plurality of processors is the executing processor; and transferring data or a command between the executing processor designated in the LastProcessor indicator and the I/O device in response to the I/O instruction.

Claim 10

Dependent Claim 32 words

A method as defined in claim 7 , further comprising translating the data or command to be transferred to a different format compatible with a device that receives the data or command.

Claim 11

Dependent Claim 97 words

A method as defined in claim 7 , wherein determining which of the processors in said multi-processor environment is the executing processor comprises determining which of the processors in said multi-processor environment is the executing processor by designating for each of the plurality of the processors whether an instruction address count difference between an instruction address for an I/O instruction last performed by that processor and the current instruction address for that processor is less than or equal to a predetermined number, and using this information in determining which of the processors are executing an I/O instruction.

Claim 12

Dependent Claim 54 words

A method as defined in claim 9 , further comprising, when the instruction address count difference for a particular processor is equal to one, deleting the designation of the particular processor as the executing processor unless the last I/O instruction for the particular processor designates directly or indirectly a port for the I/O device.

Claim 13

Dependent Claim 155 words

A computer program product, comprising: a computer usable medium having computer readable program code embodied therein for providing I/O functions between an appropriate processor in a multi-processor environment and an I/O device during an I/O interrupt, the computer readable program code in the computer program product comprising first computer readable program code to determine which of a plurality of processors in the multi-processor environment are executing an I/O instruction said first computer readable program code to utilize a save state area for each of the plurality of processors; second computer readable program code to determine if only one of the plurality of processors in the multi-processor environment is executing the I/O instruction, and in that case, setting a LastProcessor indicator designating the one processor as the processor executing the I/O instruction; and third computer readable program code to transfer data or a command between the processor designated by the LastProcessor indicator and the I/O device.

Claim 14

Dependent Claim 155 words

A computer program product, comprising: a computer usable medium having computer readable program code embodied therein for providing I/O functions between an appropriate processor in a multi-processor environment and an I/O device during an I/O interrupt, the computer readable program code in the computer program product comprising first computer readable program code to determine which of a plurality of processors in the multi-processor environment are executing an I/O instruction said first computer readable program code to utilize a save state area for each of the plurality of processors; second computer readable program code to determine if only one of the plurality of processors in the multi-processor environment is executing the I/O instruction, and in that case, setting a LastProcessor indicator designating the one processor as the processor executing the I/O instruction; and third computer readable program code to transfer data or a command between the processor designated by the LastProcessor indicator and the I/O device.

Claim 15

Dependent Claim 84 words

A computer program product as defined in claim 11 , wherein the first computer readable program code includes fourth computer readable program code for determining for each of the plurality of the processors whether an instruction address count difference between an instruction address for an I/O instruction last performed by that processor and the current instruction address for the processor are less than or equal to a predetermined number, and using that information in determining which of the processors are executing the I/O instruction.

Claim 16

Dependent Claim 73 words

A computer program product as defined in claim 12 , wherein the first computer readable program code includes fifth computer readable program code for determining when the instruction address count difference for a particular processor is equal to one, and deleting the designation of the particular processor as the processor executing the I/O instruction unless the last I/O instruction for the particular processor designates directly or indirectly a port for the I/O device.

Claim 17

Dependent Claim 16 words

A computer program product as defined in claim 11 , wherein the predetermined number is 2.

Claim 18

Dependent Claim 175 words

A multi-processor system, comprising: a plurality of processors, each capable of executing an I/O instruction to transfer data or a command between the plurality of processors and an I/O device; an I/O and trap hardware that issues an interrupt on the plurality of processors upon receipt of a selected I/O instruction from one of the plurality of processors and to transfer data or a command between the I/O device and said one of the plurality of processors; and a first device that provides a designation, for each of the plurality of processors, whether an instruction address count difference between an instruction address for an I/O instruction last performed by that processor and a current instruction address for that processor is less than or equal to a predetermined number, and using that information to determine which of the plurality of processors to connect to the I/O device to transfer the data or command between the I/O device and said one of the plurality of processors in response to the selected I/O instruction and making that connection.

Claim 19

Dependent Claim 175 words

A multi-processor system, comprising: a plurality of processors, each capable of executing an I/O instruction to transfer data or a command between the plurality of processors and an I/O device; an I/O and trap hardware that issues an interrupt on the plurality of processors upon receipt of a selected I/O instruction from one of the plurality of processors and to transfer data or a command between the I/O device and said one of the plurality of processors; and a first device that provides a designation, for each of the plurality of processors, whether an instruction address count difference between an instruction address for an I/O instruction last performed by that processor and a current instruction address for that processor is less than or equal to a predetermined number, and using that information to determine which of the plurality of processors to connect to the I/O device to transfer the data or command between the I/O device and said one of the plurality of processors in response to the selected I/O instruction and making that connection.

Claim 20

Dependent Claim 68 words

A multi-processor system, as defined in claim 15 , further including logic to delete the designation of a particular processor as having an instruction count difference of less than or equal to the predetermined number when the instruction address count difference for the particular processor is equal to one, unless the last I/O instruction for the particular processor designates directly or indirectly a port for the I/O device.

Claim 21

Independent Claim 163 words

A method for controlling I/O in a multi-processor environment, comprising: determining if an I/O instruction requiring an interrupt is being executed by one of a plurality of processors in the multi-processor environment to transfer data or a command between the one of the plurality of processors and an I/O device; performing an interrupt if the I/O instruction is detected; providing a designation for each of the plurality of processors in the multi-processor environment whether an instruction address count difference between an instruction address for an I/O instruction last performed by that processor and a current instruction address for that processor is less than or equal to a predetermined number; and, using said designation for each of the plurality of processors to determine which of the plurality of processors to connect to the I/O device to transfer the data or command between the I/O device and said one of the plurality of processors in response to the selected I/O instruction and making that connection.

Claim 22

Independent Claim 163 words

A method for controlling I/O in a multi-processor environment, comprising: determining if an I/O instruction requiring an interrupt is being executed by one of a plurality of processors in the multi-processor environment to transfer data or a command between the one of the plurality of processors and an I/O device; performing an interrupt if the I/O instruction is detected; providing a designation for each of the plurality of processors in the multi-processor environment whether an instruction address count difference between an instruction address for an I/O instruction last performed by that processor and a current instruction address for that processor is less than or equal to a predetermined number; and, using said designation for each of the plurality of processors to determine which of the plurality of processors to connect to the I/O device to transfer the data or command between the I/O device and said one of the plurality of processors in response to the selected I/O instruction and making that connection.

Claim 23

Dependent Claim 64 words

A method as defined in claim 17 , further comprising deleting the designation of a processor as having an instruction count difference of less than or equal to the predetermined number when the instruction address count difference for a particular processor is equal to one, unless the last I/O instruction for the particular processor designates directly or indirectly a port for the I/O device.

Claim 24

Dependent Claim 150 words

A computer program product, comprising: a computer usable medium having computer readable program code embodied therein for providing I/O functions between an appropriate processor in a multi-processor environment and an I/O device during an I/O interrupt, the computer readable program code in the computer program product comprising first computer readable program code to provide a designation for each of a plurality of the processors in the multi-processor environment whether an instruction address count difference between an instruction address for an I/O instruction last performed by that processor and a current instruction address for that processor is less than or equal to a predetermined number; and second computer readable program code to use said designation for each of the plurality of processors in determining which processor to connect to the I/O device to transfer the data or command between the I/O device and the appropriate processor and to make this connection.

Claim 25

Dependent Claim 150 words

A computer program product, comprising: a computer usable medium having computer readable program code embodied therein for providing I/O functions between an appropriate processor in a multi-processor environment and an I/O device during an I/O interrupt, the computer readable program code in the computer program product comprising first computer readable program code to provide a designation for each of a plurality of the processors in the multi-processor environment whether an instruction address count difference between an instruction address for an I/O instruction last performed by that processor and a current instruction address for that processor is less than or equal to a predetermined number; and second computer readable program code to use said designation for each of the plurality of processors in determining which processor to connect to the I/O device to transfer the data or command between the I/O device and the appropriate processor and to make this connection.

Claim 26

Dependent Claim 74 words

A computer program product as defined in claim 19 , wherein the first computer readable program code includes third computer readable program code to determine when the instruction address count difference for a particular processor is equal to one, and to delete the designation of the particular processor as a processor executing an I/O instruction unless the last I/O instruction for the particular processor designates directly or indirectly a port for the I/O device.

Claim 27

Independent Claim 68 words

A method for servicing a software system management interrupt (SMI) initiated by an I/O instruction in a multi-processor environment, comprising: detecting the occurrence of the software SMI; determining which processor in said multi-processor environment has save state information relating to the I/O instruction indicating that that processor initiated the software SMI; and transferring information between an SMI handler and said processor determined to have initiated the software SMI.

Claim 28

Independent Claim 68 words

A method for servicing a software system management interrupt (SMI) initiated by an I/O instruction in a multi-processor environment, comprising: detecting the occurrence of the software SMI; determining which processor in said multi-processor environment has save state information relating to the I/O instruction indicating that that processor initiated the software SMI; and transferring information between an SMI handler and said processor determined to have initiated the software SMI.

Claim 29

Dependent Claim 65 words

A method as defined in claim 21 , wherein determining which processor in said multi-processor environment has save state information comprises determining which processor in said multi-processor environment has an EIP′ value in an interrupt save state area equal to an offset location where an instruction which immediately follows an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists.

Claim 30

Dependent Claim 56 words

A method as defined in claim 22 , wherein determining which processor in said multi-processor environment has save state information further comprises determining if the EIP value in a processor I/O save state area equals an offset location at which an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists.

Claim 31

Dependent Claim 55 words

A method as defined in claim 21 , wherein determining which processor in said multi-processor environment has save state information comprises determining if the EIP value in a processor I/O save state area equals an offset location at which an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists.

Claim 32

Dependent Claim 48 words

A method as defined in claim 24 , wherein determining which processor in said multi-processor environment has save state information further comprises determining if ECX, ESI and EDI values in said processor I/O save state equal the ECX, ESI, and EDI values in an interrupt save state area.

Claim 33

Independent Claim 145 words

A method for servicing a software system management interrupt (SMI) initiated by an I/O instruction in a multi-processor environment, comprising the steps of: detecting the occurrence of a software SMI; designating a processor in said multi-processor environment as having initiated the software SMI if both of the following tests, in any order, are true: 1) the processor in said multi-processor environment has an EIP′ value in an interrupt save state area equal to an offset location where an instruction which immediately follows an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists, and 2) an EIP value in an I/O save state area for the processor equals an offset location at which an I/O call instruction that initiates software SMI's in said BIOS software SMI call routine exists; and transferring information between said SMI handler and said designated processor.

Claim 34

Independent Claim 145 words

A method for servicing a software system management interrupt (SMI) initiated by an I/O instruction in a multi-processor environment, comprising the steps of: detecting the occurrence of a software SMI; designating a processor in said multi-processor environment as having initiated the software SMI if both of the following tests, in any order, are true: 1) the processor in said multi-processor environment has an EIP′ value in an interrupt save state area equal to an offset location where an instruction which immediately follows an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists, and 2) an EIP value in an I/O save state area for the processor equals an offset location at which an I/O call instruction that initiates software SMI's in said BIOS software SMI call routine exists; and transferring information between said SMI handler and said designated processor.

Claim 35

Dependent Claim 115 words

A multi-processor system, comprising: at least a first and a second processors, each capable of initiating a software-generated system management interrupt (SMI) by generating an I/O call instruction in a BIOS software SMI call routine; an SMI handler for processing system management interrupts; first logic for detecting the occurrence of a software SMI; second logic to determine, after said first logic has detected the occurrence of a software SMI, which processor in said multi-processor environment has save state information relating to the I/O call instruction which indicates that processor as having initiated the software SMI; and third logic to transfer information between said SMI handler and said processor determined to have initiated the software SMI.

Claim 36

Dependent Claim 115 words

A multi-processor system, comprising: at least a first and a second processors, each capable of initiating a software-generated system management interrupt (SMI) by generating an I/O call instruction in a BIOS software SMI call routine; an SMI handler for processing system management interrupts; first logic for detecting the occurrence of a software SMI; second logic to determine, after said first logic has detected the occurrence of a software SMI, which processor in said multi-processor environment has save state information relating to the I/O call instruction which indicates that processor as having initiated the software SMI; and third logic to transfer information between said SMI handler and said processor determined to have initiated the software SMI.

Claim 37

Dependent Claim 61 words

A multi-processor system as defined in claim 27 , wherein said second logic includes third logic for determining if a processor in said multi-processor environment has an EIP′ value in an interrupt save area equal to an offset location where an instruction which immediately follows an I/O call instruction that initiates software SMI's in said BIOS software SMI call routine exists.

Claim 38

Dependent Claim 51 words

A multi-processor system as defined in claim 28 , wherein said second logic includes fourth logic for determining if an EIP value in a processor I/O save state area equals an offset location at which an I/O call instruction that initiates software SMI's in said BIOS software SMI call routine exists.

Claim 39

Dependent Claim 51 words

A multi-processor system as defined in claim 27 , wherein said second logic includes fourth logic for determining if an EIP value in a processor I/O save state area equals an offset location at which an I/O call instruction that initiates software SMI's in said BIOS software SMI call routine exists.

Claim 40

Dependent Claim 144 words

A computer program product, comprising a computer usable medium having computer readable program code embodied therein to determine which processor in a multi-processor environment initiated a software system management interrupt (SMI) by generating a particular I/O instruction and to provide communication between an SMI handler and that processor, the computer readable program code in the computer program product comprising: first computer readable program code to detect the occurrence of a software SMI; second computer readable program code to designate, after said first computer readable program code means has detected the occurrence of a software SMI, which processor in said multi-processor environment has save state information relating to the particular I/O instruction which indicates that processor as having initiated the software SMI; and third computer readable program code to transfer information between said SMI handler and said processor determined to have initiated the software SMI.

Claim 41

Dependent Claim 144 words

A computer program product, comprising a computer usable medium having computer readable program code embodied therein to determine which processor in a multi-processor environment initiated a software system management interrupt (SMI) by generating a particular I/O instruction and to provide communication between an SMI handler and that processor, the computer readable program code in the computer program product comprising: first computer readable program code to detect the occurrence of a software SMI; second computer readable program code to designate, after said first computer readable program code means has detected the occurrence of a software SMI, which processor in said multi-processor environment has save state information relating to the particular I/O instruction which indicates that processor as having initiated the software SMI; and third computer readable program code to transfer information between said SMI handler and said processor determined to have initiated the software SMI.

Claim 42

Dependent Claim 66 words

A computer program product as defined in claim 31 , wherein said second computer readable program code means comprises code for determining if a processor in said multi-processor environment has an EIP′ value in an interrupt save state area equal to an offset location where an instruction which immediately follows an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists.

Claim 43

Dependent Claim 55 words

A computer program product as defined in claim 31 , wherein said second computer readable program code means comprises code for determining if an EIP value in a processor I/O save state area equals an offset location at which an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists.

Claim 44

Dependent Claim 206 words

A computer program product, comprising: a computer usable medium having computer readable program code means embodied therein for determining which processor in a multi-processor environment initiated a software system management interrupt (SMI) and providing communication between an SMI handler and that processor, the computer readable program code means in the computer program product comprising: first computer readable program code means for detecting the occurrence of a software SMI; second computer readable program code means for designating, after said first computer readable program code means has detected the occurrence of a software SMI, a processor in said multi-processor environment as having initiated the software SMI if both of the following tests, in any order, are true: 1) the processor in said multi-processor environment has an EIP′ value in an interrupt save state area equal to an offset location where an instruction which immediately follows an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists, and 2) the EIP value in an I/O save state area for the processor equals an offset location at which an I/O call instruction that initiates software SMI's in said BIOS software SMI call routine exists; and transferring information between the SMI handler and said designated processor.

Claim 45

Dependent Claim 206 words

A computer program product, comprising: a computer usable medium having computer readable program code means embodied therein for determining which processor in a multi-processor environment initiated a software system management interrupt (SMI) and providing communication between an SMI handler and that processor, the computer readable program code means in the computer program product comprising: first computer readable program code means for detecting the occurrence of a software SMI; second computer readable program code means for designating, after said first computer readable program code means has detected the occurrence of a software SMI, a processor in said multi-processor environment as having initiated the software SMI if both of the following tests, in any order, are true: 1) the processor in said multi-processor environment has an EIP′ value in an interrupt save state area equal to an offset location where an instruction which immediately follows an I/O call instruction that initiates software SMI's in a BIOS software SMI call routine exists, and 2) the EIP value in an I/O save state area for the processor equals an offset location at which an I/O call instruction that initiates software SMI's in said BIOS software SMI call routine exists; and transferring information between the SMI handler and said designated processor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2006-05-26	2006-11-25	2007-05-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2010-05-26	2010-11-25	2011-05-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2014-05-26	2014-11-25	2015-05-27	$7700.00	Window Closed / Lapsed

Apparatus and method for emulating an I/O instruction for the correct processor and for servicing software SMI's in a multi-processor environment

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag