EP0446077A2
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EP
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A control system for multi-processor system
Assignee: Fujitsu Ltd
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Filing: 1991-03-11
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Granted: —
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Expires: 2011-03-11
Abstract
Abstract An input/output request control system in a multi-processor system includes a plurality of information processing modules (PM). The system comprises a plurality of input/output adapters (ADP) commonly used by each of said information processing modules and a plurality of input/output devices (DVC) divided to be controlled by respective input/output adapters. An input/output request maintaining table (LDVC) manages input/output requests from respective information processing modules for each of the input/output devices controlled by said information processing modules by using a queue. Input/output requests from respective information processing modules are processed based on the state of the input/output request maintaining table and the input/output devices.
Inventors
- 👤 Makoto Kimura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:56
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
109 words
An input/output request control system in a multi-processor system including a plurality of information processing modules (PM), said system comprising: a plurality of input/output adapters (ADP) commonly used by each of said information processing modules; a plurality of input/output devices (DVC) divided to be controlled by respective input/output adapters; means for providing an input/output request maintaining table (LDVC) for managing input/output requests from respective information processing modules for each of said input/output devices controlled by said information processing modules by using a drive queue; and means for processing input/output requests from respective information processing modules based on a state of said input/output request maintaining table and the input/output devices.
Claim 2
Dependent Claim
33 words
The input/output request control system according to claim 1, wherein PDVCs are provided in accordance with said DVCs and said PDVCs form a PDVC drive queue in the order of access to DVBUS.
Claim 3
Dependent Claim
52 words
The input/output request control system according to claim 1, wherein said input/output request maintaining table stores input/output requests from a plurality of PMs to the same DVC in respective cells of a row corresponding to the same DVC, thereby enabling said cells to form an LDVC drive queue in a predetermined order.
Claim 4
Dependent Claim
105 words
The input/output request control system according to claim 3, wherein PDVCs are provided corresponding to said respective DVCs, the DVCs corresponding to respective rows of said input/output request maintaining table are controlled by a PDVC queue, and when the LDVC reaches the head of the LDVC queue, the LDVC at the head of the LDVC queue enters the PDVC queue and when the PDVC comes to the head of the PDVC queue, an execution of the input/output starts, whereby the input/output request is executed when the input/output request reaches the head of the LDVC drive queue and further reaches the head of the PDVC queue.
Claim 5
Dependent Claim
146 words
The input/output request control system according to claim 4, wherein the states of said LDVC comprise IDLE, in which nothing is done; WAIT, in which the availability of PDVC is awaited; WORK, in which the LDVC comes to the head of the queue and executes the input/output operation; IRQW, in which LDVC is entered into the interrupt queue and awaits its turn to issue an IRQ bus command; IRQEX, in which LDVC is connected to the head of interrupt queue, PMIC is connected to the head of PMIC interrupt queue, an IRQ bus command is issued and notification of acceptance by PM is awaited; and IACKW, in which the interrupt request is accepted by the PM and the IACK bus command is awaited by ADP, whereby the input/output request is associated with the interrupt request relating to a completion of an execution of the input/output request.
Claim 6
Dependent Claim
49 words
The input/output request control system according to claim 4, wherein said PDVC comprises IDLE, in which nothing is done; WAIT, in which the availability of DVBUS is awaited; WORK, in which the input/output operation is executed; and DISC, in which the DVC is operating and the DVBUS is disconnected.
Claim 7
Dependent Claim
102 words
The input/output request control system according to claim 4, wherein said ADP comprises means for accepting an input/output command when the input/output command arrives, means for executing an input/output command when the input/output command does not arrive or when a PDVC in a WAIT state exits upon a completion of acceptance of the input/output command and for performing an interrupt operation to the PM upon a completion of an input/output operation, and means for performing a reconnection process when the PDVC in a WAIT state does not exist or when the reconnection request is made upon an execution of said input/output command.
Claim 8
Dependent Claim
114 words
An I/O request control system according to claim 7, wherein said input/output request accepting means comprising means for rejecting an acceptance of an input/output request when IACK is not issued and LDVCnm is in a state other than IDLE, means for responding to PM by a completion of the input/output request receipt when IACK is not issued and LDVCnm is in an IDLE state, means for changing the state of LDVCmn to WAIT and adding LDVCmn to the LDVC queue, means for changing PDVCm to WAIT when PDVCm is in an IDLE state and adding PDVCm to PDVC drive queue, and means for making LDVCnm in an interrupt state IDLE when IACK is issued.
Claim 9
Dependent Claim
146 words
The input/output request control system according to claim 7, wherein said input/output command executing means comprises means for changing the state of PDVCm to WORK when DVBUS is available and changing the state of LDVCm to WORK, means for executing an input/output operation, means for changing the state of PDVCm to DISC when the input/output operation is not completed and removing PDVCm from the PDVC queue, means for removing LDVCnm from LDVC drive queue and performing an interrupt process when all the input/output operations are completed, means for changing the state of PDVCm to IDLE when the length of the LDVC drive queue is 0 and removing PDVCm from said PDVC drive queue, and means for changing the state of PDVCm to WAIT when the length of the LDVC drive queue is not 0 and adding the PDVCm to the last of the PDVC drive queue.
Claim 10
Dependent Claim
95 words
The interrupt request control system according to claim 9, wherein said interrupt process comprises means for judging the length of the PMIC interrupt queue, means for connecting the interrupt request to the LDVC interrupt queue of the PMICn when the length of the PMIC interrupt queue is not 0 and means for connecting said interrupt request to the head of PMIC queue and further connecting said interrupt request to the head of LDVC interrupt queue of PMICn when the length of PMIC interrupt queue is 0 and for instructing that an interrupt command be issued.
Claim 11
Dependent Claim
133 words
The interrupt request control system according to claim 9, wherein said interrupt process means comprises means for removing the LDVC at the head from the LDVC interrupt queue when the interrupt bus command is accepted, means for removing a PMIC from PMIC queue when the length of LDVC interrupt queue is 0, means for making the state of the next PMIC ACTIVE when the length of the PMIC interrupt queue is not 0, making the LDVC at the head IRQEX and issuing the interrupt command, means for returning to an original process when the length of the PMIC interrupt queue is 0 and means for connecting PMIC to the end of the PMIC queue when the interrupt bus command is not accepted or the length of the LDVC interrupt queue is not 0.
Claim 12
Dependent Claim
100 words
An interrupt request control system in a multiprocessor system including a plurality of information processing modules (PM), said system comprising: a plurality of input/output adapters (ADP) commonly used by each of said information processing modules; a plurality of input/output devices (DVC) divided to be controlled by respective input/output adapters; means for providing an interrupt request maintaining table for managing interrupt requests from respective input/output devices to each of said information processing modules by using a queue; and means for processing interrupt requests of respective input/output devices based on the state of said interrupt request maintaining table and the input/output devices.
Claim 13
Dependent Claim
33 words
The interrupt request control system according to claim 12, wherein PMICs are provided in accordance with said PMs and said PMICs form a PMIC interrupt queue in the order of access to IOBUS.
Claim 14
Dependent Claim
50 words
The interrupt request control system according to claim 12, wherein said interrupt request maintaining table stores interrupt requests from a plurality of DVCs to the same PM in respective cells of a row corresponding to the same PM, thereby enabling said cells to form a queue in a predetermined order.
Claim 15
Dependent Claim
76 words
The interrupt request control system according to claim 12, wherein PMICs are provided corresponding to said respective PMs, said PMs corresponding to respective rows of said input/output request maintaining table are controlled by a PMIC queue, and when the LDVC reaches the head of the LDVC queue, the LDVC at the head of the LDVC queue enters the PMIC queue and when the PMIC comes to the head of the PMIC queue, an interrupt execution starts.
Claim 16
Dependent Claim
125 words
The interrupt request control system according to claim 15, wherein the state of said LDVC comprises IDLE, in which nothing is done; WAIT, in which the availability of PDVC is awaited; WORK, in which the LDVC comes to the head of the queue and executes the input/output operation; IRQW, in which LDVC is entered into the interrupt queue and awaits its turn to issue an IRQ bus command; IRQEX, in which LDVC is connected to the head of interrupt queue, PMIC is connected to the head of PMIC interrupt queue, an IRQ bus command is issued and notification of acceptance by PM is awaited; and IACKW, in which the interrupt request is accepted by the PM and the IACK bus command is awaited by ADP.
Claim 17
Dependent Claim
38 words
The interrupt request control system according to claim 15, wherein said PDVC comprises IDLE, in which nothing is done; WAIT, in which the availability of DVBUS is awaited; and WORK, in which the input/output operation is being executed.
Claim 18
Dependent Claim
138 words
The interrupt request control system according to claim 12, wherein said interrupt process comprises means for judging the length of the PMIC interrupt queue when the state of PMIC is IDLE, means for making the state of PMIC WAIT, connecting the interrupt request to PMIC queue and connecting the interrupt request to the LDVC interrupt queue of the PMICn when the length of the PMIC interrupt queue is not 0, means for connecting said interrupt request to the head of PMIC queue and further connecting said interrupt request to the head of LDVC interrupt queue of PMICn when the length of PMIC interrupt queue is 0 and for instructing that an interrupt command be issued and means for connecting said interrupt request to an LDVC interrupt queue of PMICn when the state of PMICn is WAIT or ACTIVE.
Claim 19
Dependent Claim
133 words
The interrupt request control system according to claim 12, wherein said interrupt process means comprises means for removing the LDVC at the head from the LDVC interrupt queue when the interrupt bus command is accepted, means for removing a PMIC from PMIC queue when the length of LDVC interrupt queue is 0, means for making the state of the next PMIC ACTIVE when the length of the PMIC interrupt queue is not 0, making the LDVC at the head IRQEX and issuing the interrupt command, means for returning to an original process when the length of the PMIC interrupt queue is 0 and means for connecting PMIC to the end of the PMIC queue when the interrupt bus command is not accepted or the length of the LDVC interrupt queue is not 0.
References Cited (Backward Citations)
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