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Patent US6567303B1 successfully refreshed from Google Patents.
US6567303B1
Expired / Lapsed
US
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Charge injection
Assignee: Longitude Flash Memory Solutions Ltd
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Filing: 2002-01-16
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Granted: 2003-05-20
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Expires: 2022-01-16
Abstract
Abstract A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
Inventors
- 👤 Darlene G. Hamilton
- 👤 Janet S. Y. Wang
- 👤 Narbeh Derhacobian
- 👤 Tim Thurgate
- 👤 Michael K. Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:41
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; G11C11/00; G11C11/56; G11C11/5671; G11C16/04; G11C16/0466; G11C16/0475; G11C16/3436; G11C16/344; G11C16/3445; G11C16/10
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
114 words
A method of programming bits in an ONO dual bit memory cell operating in a double bit mode, the method comprising: applying a program pulse to at least one bit of the dual bit memory cell by concurrently applying a voltage to a drain of the at least one bit and applying a voltage to a gate of the at least one bit; verifying a delta VT of the at least one bit is within a range of about 2.0 to about 2.5 volts; and repeating the step of applying a program pulse until the delta VT of the at least one bit is within the range of about 2.0 to about 2.5 volts.
Claim 2
Independent Claim
114 words
A method of programming bits in an ONO dual bit memory cell operating in a double bit mode, the method comprising: applying a program pulse to at least one bit of the dual bit memory cell by concurrently applying a voltage to a drain of the at least one bit and applying a voltage to a gate of the at least one bit; verifying a delta VT of the at least one bit is within a range of about 2.0 to about 2.5 volts; and repeating the step of applying a program pulse until the delta VT of the at least one bit is within the range of about 2.0 to about 2.5 volts.
Claim 3
Dependent Claim
48 words
The method of claim 1 , the step of applying a program pulse comprising concurrently applying a voltage in a range of about 5 to about 5.5 volts to the drain and applying a voltage in a range of about 9.25 to about 9.5 volts to the gate.
Claim 4
Dependent Claim
16 words
The method of claim 2 , the program pulse having a duration of about 0.5 microseconds.
Claim 5
Dependent Claim
44 words
The method of claim 1 , the ONO dual bit memory cell operating in a double bit mode wherein the ONO dual bit memory cell has a normal bit and a complimentary bit wherein both the normal bit and the complimentary bit is programmed.
Claim 6
Dependent Claim
25 words
The method of claim 4 , further comprising: performing a verify erase of the normal bit; and performing a verify erase of the complimentary bit.
Claim 7
Dependent Claim
40 words
The method of claim 5 , the step of verify erase of the normal bit and complimentary bit comprising repeating steps of verifying and applying erase pulses until both the normal bit and complimentary bit are in a blank state.
Claim 8
Dependent Claim
53 words
The method of claim 6 , further comprising verifying if a VT of the normal bit is below a minimum allowable VT for the blank state and applying a soft program pulse to the normal bit if the VT of the normal bit is below the minimum allowable VT for the blank state.
Claim 9
Dependent Claim
53 words
The method of claim 7 , further comprising verifying if a VT of the complimentary bit is below the minimum allowable VT for the blank state and applying a soft program pulse to the complimentary bit if the VT of the complimentary bit is below the minimum allowable VT for the blank state.
Claim 10
Dependent Claim
61 words
The method of claim 8 , further comprising verifying if the VT of the normal bit is above a maximum allowable VT for a blank state caused by applying a soft program pulse to the normal bit and applying at least one erase pulse if the VT of the normal bit is above the maximum allowable VT for the blank state.
Claim 11
Dependent Claim
61 words
The method of claim 9 , further comprising verifying if the VT of the complimentary bit is above the maximum allowable VT for the blank state caused by applying a soft program pulse to the complimentary bit and applying at last one erase pulse if the VT of the complimentary bit is above the maximum allowable VT for the blank state.
Claim 12
Independent Claim
155 words
A method of determining programming parameters for programming bits of an array of ONO dual bit memory cells operating in a double bit mode, the method comprising: performing a predetermined number of program and erase cycles followed by an accelerated bake on at least one array in a lot; determining a charge loss of at least one bit of the at least one array after the program and erase cycles and accelerated bake; determining an increase in delta VT to accommodate for the charge loss of the at least one bit of the at least one array for additional arrays in the lot; and determining programming parameters to allow programming of the cells at the increased delta VT in an acceptable time, the programming parameters comprising a programming pulse width, a potential of a programming pulse at a gate of a cell and a potential of the programming pulse at a drain of the cell.
Claim 13
Independent Claim
155 words
A method of determining programming parameters for programming bits of an array of ONO dual bit memory cells operating in a double bit mode, the method comprising: performing a predetermined number of program and erase cycles followed by an accelerated bake on at least one array in a lot; determining a charge loss of at least one bit of the at least one array after the program and erase cycles and accelerated bake; determining an increase in delta VT to accommodate for the charge loss of the at least one bit of the at least one array for additional arrays in the lot; and determining programming parameters to allow programming of the cells at the increased delta VT in an acceptable time, the programming parameters comprising a programming pulse width, a potential of a programming pulse at a gate of a cell and a potential of the programming pulse at a drain of the cell.
Claim 14
Dependent Claim
38 words
The method of claim 11 , the programming pulse width being about 0.5 microseconds at a selected gate potential of about 9.25 to about 9.5 volts and a selected drain potential of about 5.0 to about 5.5 volts.
Claim 15
Dependent Claim
32 words
The method of claim 12 , further comprising a step of programming a command logic and state machine for programming to an increased delta VT utilizing the selected drain and gate potentials.
Claim 16
Dependent Claim
48 words
The method of claim 12 , the array of ONO dual bit memory cells operating in a double bit mode wherein each of the ONO dual bit memory cells have a normal bit and a complimentary bit wherein both the normal bit and the complimentary bit is programmed.
Claim 17
Independent Claim
214 words
A system for programming bits in an array of ONO dual bit memory cells operating in a double bit mode, the system comprising: an array of dual bit flash memory cells; an address decoder component coupled to the array of ONO dual bit flash memory cells, the address decoder component providing access to bits of the ONO dual bit flash memory cells; a voltage generator to provide appropriate voltages for performing programming and erasing of bits of the ONO dual bit flash memory cells; and a command logic component including a state machine, the command logic component and state machine being coupled to the array and the address component and being operable to control the voltage generator, the command logic component and state machine having a capability to program at least one bit by selecting the at least one bit and applying a program pulse that applies a first voltage to a drain and a second voltage to a gate of a cell, verifying a delta VT of the at least one bit is within a range of about 2.0 to about 2.5 volts and repeating the step of applying a program pulse until the delta VT of the at least one bit is within the range of about 2.0 to about 2.5 volts.
Claim 18
Independent Claim
214 words
A system for programming bits in an array of ONO dual bit memory cells operating in a double bit mode, the system comprising: an array of dual bit flash memory cells; an address decoder component coupled to the array of ONO dual bit flash memory cells, the address decoder component providing access to bits of the ONO dual bit flash memory cells; a voltage generator to provide appropriate voltages for performing programming and erasing of bits of the ONO dual bit flash memory cells; and a command logic component including a state machine, the command logic component and state machine being coupled to the array and the address component and being operable to control the voltage generator, the command logic component and state machine having a capability to program at least one bit by selecting the at least one bit and applying a program pulse that applies a first voltage to a drain and a second voltage to a gate of a cell, verifying a delta VT of the at least one bit is within a range of about 2.0 to about 2.5 volts and repeating the step of applying a program pulse until the delta VT of the at least one bit is within the range of about 2.0 to about 2.5 volts.
Claim 19
Dependent Claim
39 words
The system of claim 15 , the voltage to the drain being in a range of about 5.0 to about 5.5 volts and the voltage to the gate being in a range of about 9.25 to about 9.5 volts.
Claim 20
Dependent Claim
16 words
The system of claim 16 , the program pulse having a duration of about 0.5 microseconds.
Claim 21
Dependent Claim
47 words
The method of claim 15 , the array of ONO dual bit memory cells operating in a double bit mode wherein each of the ONO dual bit memory cells have a normal bit and a complimentary bit wherein both the normal bit and complimentary bit are programmed.
Claim 22
Dependent Claim
68 words
The system of claim 18 , the command logic component further being operable to receive an erase command and execute an erase algorithm that programs normal bits of the memory cells to a delta VT within the range of 2.0 to 2.5 volts, performs a verify erase of the normal bits in the normal columns and performs a verify erase of the complimentary bits in adjacent complimentary columns.
Claim 23
Dependent Claim
62 words
The system of claim 19 , the erase algorithm being further adapted to continue the verify erase of the normal bits in the normal columns and the complimentary bits in the adjacent complimentary columns for the normal and complimentary bits in a sector of memory until all of the bits have a VT below a maximum allowable VT for a blank state.
Claim 24
Dependent Claim
69 words
The system of claim 20 , the erase algorithm being further operable to verify if the VT of the bits in the normal columns are below a minimum allowable VT for the blank state and applying a soft program pulse via the voltage generator to the bits in the normal columns if the VT of any of the bits are below the minimum allowable VT for the blank state.
Claim 25
Dependent Claim
71 words
The system of claim 21 , the erase algorithm being further operable to verify if the VT of the bits in the adjacent complimentary columns are below the minimum allowable VT for the blank state and applying a soft program pulse via the voltage generator to the bits in the adjacent complimentary columns if the VT of any of the bits are below the minimum allowable VT for the blank state.
Claim 26
Dependent Claim
64 words
The system of claim 22 , the erase algorithm being further performing a verify erase of bits in normal columns and performing a verify erase of complimentary bits in adjacent complimentary columns if any of the bits in the normal columns and the adjacent complimentary columns have a VT above the maximum allowable VT for the blank state caused by the soft program pulse.
Claim 27
Independent Claim
56 words
A system for programming bits in an ONO dual bit memory cell, comprising: means for programming bits in the ONO dual bit memory cell to a delta VT within a range of 2.0 to 2.5 volts; and means for verifying that the delta VT of programmed bits are within the range of 2.0 to 2.5 volts.
Claim 28
Independent Claim
56 words
A system for programming bits in an ONO dual bit memory cell, comprising: means for programming bits in the ONO dual bit memory cell to a delta VT within a range of 2.0 to 2.5 volts; and means for verifying that the delta VT of programmed bits are within the range of 2.0 to 2.5 volts.
Claim 29
Dependent Claim
89 words
The method of claim 24 , the means for programming bits in the ONO dual bit memory cell to a delta VT within the range of 2.0 to 2.5 volts being further applying a programming pulse to a bit in the cell having a duration of about 0.5 microseconds at a voltage to a drain of the cell being in a range of about 5.0 to about 5.5 volts and a voltage to a gate of the cell being in a range of about 9.25 to about 9.5 volts.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-05-19 | 2006-11-18 | 2007-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-19 | 2010-11-18 | 2011-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-19 | 2014-11-18 | 2015-05-20 | $7700.00 | Window Closed / Lapsed |