Patent US6567290B2 successfully refreshed from Google Patents.
US6567290B2
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US
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High-speed low-power semiconductor memory architecture
Assignee: Mosaic Systems Inc
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Filing: 2001-06-01
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Granted: 2003-05-20
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Expires: 2021-06-01
Abstract
Abstract An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
Inventors
- 👤 Suren A. Alexanian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C7/00; G11C7/18; G11C5/00; G11C5/02; G11C5/025; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
123 words
A semiconductor memory comprising: a first array block having at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend, each of the two sub-array blocks comprising at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend, the first group of local interconnect lines being configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines being configured to carry a subset of the input information, wherein the first group of local interconnect lines extends orthogonally to the second group of local interconnect lines.
Claim 2
Dependent Claim
123 words
A semiconductor memory comprising: a first array block having at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend, each of the two sub-array blocks comprising at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend, the first group of local interconnect lines being configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines being configured to carry a subset of the input information, wherein the first group of local interconnect lines extends orthogonally to the second group of local interconnect lines.
Claim 3
Dependent Claim
74 words
The memory of claim 1 further comprising a first higher-level array block, the first higher-level array block comprising: at least a second array block and said first array block, said second array block being substantially similar to said first array block; and a third interconnect routing channel through which a third group of local interconnect lines extend, the third group of local interconnect lines being configured to carry a superset of the input information.
Claim 4
Dependent Claim
23 words
The memory of claim 1 wherein the first group of local interconnect lines extends orthogonally to the second group of local interconnect lines.
Claim 5
Dependent Claim
21 words
The memory of claim 1 wherein the first interconnect routing channel extends a longer distance than the second interconnect routing channel.
Claim 6
Dependent Claim
84 words
The memory of claim 1 further comprising a first decoding circuit configured to resolve address bits sufficient to select one of the at least two sub-array blocks, and a second decoding circuitry configured to resolve a remaining subset of the address bits sufficient to select one of the at least two lower-level sub-array blocks in the selected one of the at least two sub-array blocks, the selected one of the at least two lower-level sub-array blocks comprising memory locations corresponding to the address bits.
Claim 7
Dependent Claim
56 words
The memory of claim 5 wherein the first group of local interconnect lines are configured to carry at least the address bits, and the second group of local interconnect lines are configured to carry at least the remaining subset of the address bits and one or more of decoded signals provided by the first decoding circuit.
Claim 8
Dependent Claim
35 words
The memory of claim 5 wherein: the first interconnect routing channel includes the first decoding circuit; and the second interconnect routing channel in each of the two sub-array blocks includes the corresponding second decoding circuit.
Claim 9
Dependent Claim
33 words
The memory of claim 5 wherein the first interconnect routing channel includes the first decoding circuit and a portion or all of the second decoding circuit for each of the two sub-array blocks.
Claim 10
Dependent Claim
40 words
The memory of claim 1 wherein: the first interconnect routing channel is located between the two sub-array blocks; and the second interconnect routing channel in each of the two sub-array blocks is located between the corresponding two lower-level sub-array blocks.
Claim 11
Dependent Claim
46 words
The memory of claim 9 wherein the first group of local interconnect lines are from a metal layer such that a number of the interconnect lines in the first group of local interconnect lines are routed over a portion of each of the two sub-array blocks.
Claim 12
Dependent Claim
55 words
The memory of claim 9 wherein the second group of local interconnect lines in each of the two sub-array blocks are from a metal layer such that a number of the interconnect lines in the second group of local interconnect lines are routed over a portion of each of the corresponding two lower-level sub-array blocks.
Claim 13
Dependent Claim
84 words
The memory of claim 1 wherein: each lower-level sub-array block comprises a plurality of memory cell array blocks, each memory cell array block having a plurality of memory cells arranged along a predesignated number of rows and columns; and first and second adjacent memory cell array blocks are coupled to a data transfer block configured to selectively transfer data to or from selected ones of the plurality of memory cells in one or both of the first and second adjacent memory cell array blocks.
Claim 14
Dependent Claim
67 words
The memory of claim 12 wherein each lower-level sub-array block further comprises a plurality of data lines extending over the corresponding memory cell array blocks, the data lines being coupled to the data transfer block so that in a memory access operation data is transferred between the data lines and one or both of the first and second memory cell array blocks via the data transfer block.
Claim 15
Dependent Claim
70 words
The memory of claim 13 wherein the data transfer block comprises: a plurality of sense amplifiers; and a column multiplexer configured to selectively transfer data from selected ones of the plurality of memory cells in one or both of the first and second adjacent memory cell array blocks to the plurality of sense amplifiers, wherein the plurality of sense amplifiers are coupled between the column multiplexer and the data lines.
Claim 16
Dependent Claim
25 words
The memory of claim 12 wherein every two adjacent memory cell array blocks in each lower-level sub-array block are constructed in a mirror image fashion.
Claim 17
Dependent Claim
19 words
The memory of claim 12 wherein each lower-level sub-array block includes at least one redundant memory cell array block.
Claim 18
Dependent Claim
46 words
The memory of claim 16 wherein the at least one redundant memory cell array block is configured so that a memory cell array block of a lower-level sub-array block having one or more defective cells can be replaced with the corresponding redundant memory cell array block.
Claim 19
Dependent Claim
50 words
The memory of claim 16 wherein the at least one redundant memory cell array block is configured so that a defective row or column in a memory cell array block of a lower-level sub-array block can be replaced with a row or column of the corresponding redundant cell array block.
Claim 20
Dependent Claim
32 words
The memory of claim 12 wherein at least one of the memory cell array blocks in each of the lower-level sub-array blocks includes one or more redundant rows and/or columns of cells.
Claim 21
Dependent Claim
73 words
The memory of claim 19 wherein the one or more redundant rows and/or columns of cells in the at least one of the memory cell array blocks are configured so that a defective row or column of cells in any one of the memory cell array blocks of a lower-level sub-array block can be replaced with a redundant row or column of the corresponding at least one of the memory cell array blocks.
Claim 22
Dependent Claim
86 words
The memory of claim 12 wherein: each of the memory cell array blocks in each of the lower-level sub-array blocks includes one or more redundant rows and/or columns of cells; and the one or more redundant rows and/or columns of cells in each memory cell array block are configured so that a defective row or column of cells in a first memory cell array block of a lower-level sub-array block can be replaced with a redundant row or column of the first memory cell array block.
Claim 23
Dependent Claim
74 words
The memory of claim 12 wherein: the first interconnect routing channel or each of the second interconnect routing channels includes at least one redundant block of memory cells; and each redundant block of memory cells is configured so that one or more defective memory cells in any of the plurality of memory cell array blocks can be replaced with one or more memory cells in the at least one redundant block of memory cells.
Claim 24
Dependent Claim
73 words
The memory of claim 1 wherein: each lower-level sub-array block comprises a plurality of memory cells arranged along a predesignated number of rows and columns; each cell along each row has one or more terminals coupled together to form a wordline extending along the corresponding row of cells; and each cell along each column has one or more other terminals coupled to one or more bitlines extending along the corresponding column of cells.
Claim 25
Dependent Claim
36 words
The memory of claim 23 wherein each lower-level sub-array block further comprises a data transfer block configured to selectively transfer data between selected ones of the plurality of memory cells and a plurality of data lines.
Claim 26
Dependent Claim
57 words
The memory of claim 24 wherein each data transfer block comprises a plurality of sense amplifiers coupled between the plurality of memory cells in the corresponding lower-level sub-block and the plurality of data lines to amplify signals received from the selected ones of said plurality of memory cells and provide the amplified signals on said data lines.
Claim 27
Dependent Claim
37 words
The memory of claim 25 wherein each data transfer block further includes a column multiplexer configured to selectively couple the plurality of columns of cells in the corresponding lower-level sub-block to the corresponding plurality of sense amplifiers.
Claim 28
Dependent Claim
17 words
The memory of claim 23 wherein the plurality of memory cells are volatile or non-volatile memory cells.
Claim 29
Dependent Claim
21 words
The memory of claim 1 wherein the input information includes address bit information for accessing memory locations in the semiconductor memory.
Claim 30
Dependent Claim
64 words
The memory of claim 1 wherein: each lower-level sub-array block has a first side extending parallel to the second group of local interconnect lines and a second side extending parallel to the first group of local interconnect lines; and each lower-level sub-array block is coupled to receive decoded address signals along the first side and to receive or transmit data along the second side.
Claim 31
Dependent Claim
34 words
The memory of claim 1 wherein: the two sub-array blocks are constructed in a mirror image fashion; and the two lower-level sub-array blocks in each sub-array block are constructed in a mirror image fashion.
Claim 32
Dependent Claim
39 words
The memory of claim 1 being configured so that in a memory access a selected one of the at least two lower-level sub-array blocks in a selected one of the at least two sub-array blocks transmits or receives data.
Claim 33
Dependent Claim
31 words
The memory of claim 1 wherein each of the first and second groups of local interconnect lines is configured to carry at least address signals, decoded address signals, and data signals.
Claim 34
Dependent Claim
35 words
The memory of claim 1 wherein the first group of local interconnect lines includes a greater number of interconnect lines than the second group of local interconnect lines in each of the two sub-array blocks.
Claim 35
Dependent Claim
37 words
The memory of claim 1 wherein a predesignated number of interconnect lines extending through the first interconnect routing channel have a wider width than a predesignated number of interconnect lines extending through the second interconnect routing channel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-05-19 | 2006-11-18 | 2007-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-19 | 2010-11-18 | 2011-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-19 | 2014-11-18 | 2015-05-20 | $7700.00 | Window Closed / Lapsed |