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US6563196B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor wafer, semiconductor device and manufacturing method therefor

Assignee: Renesas Electronics Corp
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Filing: 2001-07-26
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Granted: 2003-05-13
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Expires: 2021-07-26
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Abstract

Abstract The invention aims to easily suppress chipping on the reverse face of a semiconductor when a semiconductor wafer is cut, and to make it possible to easily prevent edge contact of bonding wires. A resin film (14) is formed at the periphery of boundary regions (corresponding to 6) provided for chip separation of semiconductor chips (8). Then, the semiconductor wafer (1) is diced by cutting along the central part (corresponding to 7) of the boundary region. Furthermore, in a semiconductor device having semiconductor elements formed on a semiconductor substrate, the resin film (14) is formed on a part of the boundary regions provided for chip separation, matching the bonding pads (3) of each chip. Alternatively, the resin film (14) is formed with a predetermined width on the periphery of the abovementioned boundary regions. Additionally, the arrangement is such that the semiconductor substrate (9) and the abovementioned wires do not touch when bonding wires (16) are connected at the time of mounting the semiconductor chips.

Inventors

  • 👤 Yuichi Miyagawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 13:18
CPC Classifications
H; H10; H10P; H10P54/00; H10W; H10W74/00; H10W74/10; H10W74/131; H10W74/137; H10W90/00; H10W72/00; H10W72/071; H10W72/075; H10W72/50; H10W72/581; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W72/951; H10W90/20; H10W90/231; H10W90/291; H10W90/701; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/754; H10W90/756

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 37 words
A semiconductor wafer comprising a plurality of semiconductor chips and boundary regions provided for chip separation, wherein a resin film pattern is formed on only a part of said boundary regions matching bonding pads of each chip.
Claim 2
Dependent Claim 37 words
A semiconductor wafer comprising a plurality of semiconductor chips and boundary regions provided for chip separation, wherein a resin film pattern is formed on only a part of said boundary regions matching bonding pads of each chip.
Claim 3
Dependent Claim 40 words
A semiconductor wafer comprising a plurality of semiconductor chips and boundary regions provided for chip separation, wherein a resin film pattern is formed with a predetermined width on the periphery of said boundary regions without completely covering said boundary regions.
Claim 4
Dependent Claim 40 words
A semiconductor wafer comprising a plurality of semiconductor chips and boundary regions provided for chip separation, wherein a resin film pattern is formed with a predetermined width on the periphery of said boundary regions without completely covering said boundary regions.
Claim 5
Dependent Claim 24 words
A semiconductor wafer according to claim 2 , wherein the width of said resin film pattern is set to be greater than 10 μm.
Claim 6
Dependent Claim 40 words
A semiconductor device having semiconductor elements formed on a semiconductor substrate, wherein a resin film pattern is formed matching bonding pads of each chip on a part of boundary regions provided for chip separation without completely covering said boundary regions.
Claim 7
Dependent Claim 40 words
A semiconductor device having semiconductor elements formed on a semiconductor substrate, wherein a resin film pattern is formed matching bonding pads of each chip on a part of boundary regions provided for chip separation without completely covering said boundary regions.
Claim 8
Dependent Claim 38 words
A semiconductor device having semiconductor elements formed on a semiconductor substrate, wherein a resin film pattern is formed with a predetermined width on the periphery of boundary regions provided for chip separation without completely covering said boundary regions.
Claim 9
Dependent Claim 38 words
A semiconductor device having semiconductor elements formed on a semiconductor substrate, wherein a resin film pattern is formed with a predetermined width on the periphery of boundary regions provided for chip separation without completely covering said boundary regions.
Claim 10
Dependent Claim 24 words
A semiconductor device according to claim 5 , wherein the width of said resin film pattern is set to be greater than 10 μm.
Claim 11
Dependent Claim 27 words
A semiconductor device according to claim 4 , wherein the thickness of said resin film pattern is set to be greater than or equal to 0.1 μm.
Claim 12
Dependent Claim 24 words
The semiconductor wafer of claim 1 , wherein a first contiguous portion of said resin film pattern matches a plurality of consecutive bonding pads.
Claim 13
Dependent Claim 40 words
The semiconductor wafer of claim 8 wherein said first contiguous portion of said resin film does not cover a dicing line included in said boundary regions, said dicing line serving as a line along which said semiconductor wafer is cut.
Claim 14
Dependent Claim 39 words
The semiconductor wafer of claim 8 , wherein said first contiguous portion of said resin film covers a dicing line included in said boundary regions, said dicing line serving as a line along which said semiconductor wafer is cut.
Claim 15
Dependent Claim 21 words
The semiconductor wafer of claim 8 , wherein a second contiguous portion of said resin film matches a single bonding pad.
Claim 16
Dependent Claim 41 words
The semiconductor wafer of claim 11 , wherein said second contiguous portion of said resin film does not cover a dicing line included in said boundary regions, said dicing line serving as a line along which said semiconductor wafer is cut.
Claim 17
Dependent Claim 39 words
The semiconductor wafer of claim 11 , wherein said second contiguous portion of said resin film covers a dicing line included in said boundary regions, said dicing line serving as a line along which said semiconductor wafer is cut.
Claim 18
Dependent Claim 36 words
The semiconductor wafer of claim 1 , wherein said resin pattern does not cover a dicing line included in said boundary regions, said dicing line serving as a line along which said semiconductor wafer is cut.
Claim 19
Dependent Claim 38 words
The semiconductor wafer of claim 1 , wherein said resin pattern partially covers a portion of a dicing ling included in said boundary regions, said dicing line serving as a line along which said semiconductor wafer is cut.

References Cited (Backward Citations)

JPS62112348A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-05-12 2006-11-11 2007-05-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-05-12 2010-11-11 2011-05-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-05-12 2014-11-11 2015-05-13 $7700.00 Window Closed / Lapsed

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